Register Access Mode - Epson S1C31D50 Technical Manual

Cycle No.
QSPI_nMOD. QSPICLKn
LSBFST bit
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
1
QSDIOn3
QSDIOn2
QSDIOn1
QSDIOn0
Writing Dw[15:0] to the QSPI_nTXD register
Figure 15.4.3 Data Format Selection for Quad Transfer Mode Using the QSPI_nMOD.LSBFST Bit
(QSPI_nMOD.TMOD[1:0] bits = 0x2, QSPI_nMOD.CHLN[3:0] bits = 0x3, QSPI_nMOD.CPOL bit = 0, QSPI_nMOD.CPHA bit = 0)
15.5 Operations

15.5.1 Register Access Mode

Data can be read from or written to the external SPI/QSPI device by accessing the registers in both master and slave
modes.
In single transfer mode, transmit data are always output from the QSDIOn0 pin and receive data are always input to
the QSDIOn1 pin (the QSDIOn[3:2] pins are not used). The operations are backward compatible with legacy SPI
(e.g., synchronous serial interface of this MCU).
In dual transfer mode, transmit data are output from the QSDIOn[1:0] pins when the transfer direction is set to out-
put (QSPI_nCTL.DIR bit = 0). Receive data are input from the QSDIOn[1:0] pins when the transfer direction is set
to input (QSPI_nCTL.DIR bit = 1). The QSDIOn[3:2] pins are not used. The number of data transfer clocks is con-
figured using the QSPI_nMOD.CHLN[3:0] bits. Since two data lines are used for data transfer, the data bit length
(number of clocks) is obtained by dividing the number of transfer data bits by two.
In quad transfer mode, transmit data are output from the QSDIOn[3:0] pins when the transfer direction is set to
output (QSPI_nCTL.DIR bit = 0). Receive data are input from the QSDIOn[3:0] pins when the transfer direction
is set to input (QSPI_nCTL.DIR bit = 1). The number of data transfer clocks is configured with the QSPI_nMOD.
CHLN[3:0] bits. Since four data lines are used for data transfer, the data bit length (number of clocks) is obtained
by dividing the number of transfer data bits by four.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
1 2
Dw15 Dw11
Dw14 Dw10
Dw13 Dw9
Dw12 Dw8
Dr15 Dr11
Dr14 Dr10
Dr13 Dr9
Dr12 Dr8
Dw0 Dw4
Dw1 Dw5
Dw2 Dw6
Dw3 Dw7
Dr0 Dr4
Dr1 Dr5
Dr2 Dr6
Dr3 Dr7
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
3
Dw7
Dw6
Dw5
Dw4
Dr7
Dr6
Dr5
Dr4
Dw8
Dw9
Dw10
Dw11
Dr8
Dr9
Dr10
Dr11
Loading Dr[15:0] to the QSPI_nRXD register
4
Dw3
Dw2
Dw1
Dw0
Dr3
Dr2
Dr1
Dr0
Dw12
Dw13
Dw14
Dw15
Dr12
Dr13
Dr14
Dr15
15-9