Data Reception In Master Mode - Epson S1C31D50 Technical Manual

Data transmission using DMA
By setting the I2C_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA transfer
request is sent to the DMA controller and transmit data is transferred from the specified memory to the I2C_
nTXD register via DMA Ch.x when the I2C_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
This automates the data sending procedure from Steps 5, 6, and 8 described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the I2C_
nTXD register. For more information on DMA, refer to the "DMA Controller" chapter.
Table 16.4.2.1 DMA Data Structure Configuration Example (for Data Transmission)
End pointer Transfer source
Transfer destination I2C_nTXD register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl

16.4.3 Data Reception in Master Mode

A data receiving procedure in master mode and the I2C Ch.n operations are shown below. Figures 16.4.3.1 and
16.4.3.2 show an operation example and a flowchart, respectively.
Data receiving procedure
1. Issue a START condition by setting the I2C_nCTL.TXSTART bit to 1.
2. Wait for a transmit buffer empty interrupt (I2C_nINTF.TBEIF bit = 1) or a START condition interrupt (I2C_
nINTF.STARTIF bit = 1).
Clear the I2C_nINTF.STARTIF bit by writing 1 after the interrupt has occurred.
3. Write the 7-bit slave address to the I2C_nTXD.TXD[7:1] bits and 1 that represents READ as the data trans-
fer direction to the I2C_nTXD.TXD0 bit.
4. (When DMA is used) Configure the DMA controller and set a DMA transfer request enable bit in the I2C_
nRBFDMAEN register to 1 (DMA transfer request enabled). (This automates the data receiving procedure
Steps 5, 7, and 9.)
5. (When DMA is not used) Wait for a receive buffer full interrupt (I2C_nINTF.RBFIF bit = 1) generated
when a one-byte reception has completed.
6. Perform one of the operations below when the last or next-to-last data is received.
i. When the next-to-last data is received, write 1 to the I2C_nCTL.TXNACK bit to send a NACK after the
last data is received, and then go to Step 7.
ii. When the last data is received, read the received data from the I2C_nRXD register and set the I2C_
nCTL.TXSTOP to 1 to generate a STOP condition. Then go to Step 10.
7. (When DMA is not used) Read the received data from the I2C_nRXD register.
8．If a NACK reception interrupt (I2C_nINTF.NACKIF bit = 1) has occurred, clear the I2C_nINTF.NACKIF
bit and issue a STOP condition by setting the I2C_nCTL.TXSTOP bit to 1. Then go to Step 10 or Step 1 if
making a retry.
9. (When DMA is not used) Repeat Steps 5 to 7 until the end of data reception.
10. Wait for a STOP condition interrupt (I2C_nINTF.STOPIF bit = 1).
Clear the I2C_nINTF.STOPIF bit by writing 1 after the interrupt has occurred.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Item
Memory address in which the last transmit data is stored
0x3 (no increment)
0x0 (byte)
0x0 (+1)
0x0 (byte)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
Setting example
2
16 I C (I2C)
16-7