Table of Contents
Advertisement
15 Quad Synchronous Serial Interface
(QSPI)
15.1 Overview
The QSPI is a quad synchronous serial interface. The features of the QSPI are listed below.
• Supports both master and slave modes.
• Supports single, dual, and quad transfer modes.
• Data length: 2 to 16 clocks programmable.
• Data line drive length: 1 to 16 clocks programmable (for output direction only).
• Either MSB first or LSB first can be selected for the data format.
• Clock phase and polarity are configurable.
• Supports full-duplex communications.
• Includes separated transmit data buffer and receive data buffer registers.
• Can generate receive buffer full, transmit buffer empty, end of transmission, and overrun interrupts.
• Master mode allows use of a 16-bit timer to set baud rate.
• Slave mode is capable of being operated with the external input clock QSPICLKn only.
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by a QSPI interrupt.
• Input pins can be pulled up/down with an internal resistor.
• Low CPU overhead memory mapped access mode that can access the external Flash memory with XIP (eXecute-
In-Place) mode in the same manner as the embedded system memory.
- Memory mapped access size: 8, 16, and 32-bit access.
- 1M-byte external Flash memory mapping area starting at 0x0008_0000 that allows programmable re-mapping.
- Configurable 3 or 4-byte address cycle length.
- Single, dual, or quad transfer mode is configurable for each address, mode byte/dummy, and data cycle.
- Programmable mode bytes for both XIP mode activation and termination.
- Configurable mode byte/dummy output cycle length.
• Can issue a DMA transfer request when a receive buffer full, a transmit buffer empty, or a memory mapped ac-
cess (32-bit read) occurs.
Figure 15.1.1 shows the QSPI configuration.
Item
Number of channels
Internal clock input
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 15.1.1 QSPI Channel Configuration of S1C31D50/D51
48-pin package
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
64-pin package
80-pin package
1 channels (Ch.0)
Ch.0 ← 16-bit timer Ch.2
100-pin package
15-1
Advertisement
Table of Contents
