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19 12-BIT A/D CONVERTER (ADC12A)
Bit 0
MODEN
This bit enables the ADC12A operations.
1 (R/W): Enable ADC12A operations (The operating clock is supplied.)
0 (R/W): Disable ADC12A operations (The operating clock is stopped.)
Note: After 0 is written to the ADC12A_nCTL.MODEN bit, the ADC12A executes a terminate
processing. Before the clock source is deactivated, read the ADC12A_nCTL.MODEN bit to
make sure that it is set to 0.
ADC12A Ch.n Trigger/Analog Input Select Register
Register name
Bit
ADC12A_nTRG
15–14 –
13–11 ENDAIN[2:0]
10–8 STAAIN[2:0]
7
6
5–4 CNVTRG[1:0]
3
2–0 SMPCLK[2:0]
Note: Make sure that the ADC12A_nCTL.BSYSTAT bit is set to 0 before altering the ADC12A_nTRG reg-
ister.
Bits 15–14 Reserved
Bits 13–11 ENDAIN[2:0]
These bits set the analog input pin to be A/D converted last.
See Table 19.7.1 for the relationship between analog input pins and bit setting values.
Note: The analog input pin range to perform A/D conversion must be set as ADC12A_nTRG.
ENDAIN[2:0] bits ≥ ADC12A_nTRG.STAAIN[2:0] bits.
Bits 10–8 STAAIN[2:0]
These bits set the analog input pin to be A/D converted first.
See Table 19.7.1 for the relationship between analog input pins and bit setting values.
Bit 7
STMD
This bit selects the data alignment when the conversion results are loaded into the A/D conversion re-
sult register (ADC12A_nADD.ADD[15:0] bits).
1 (R/W): Left justify
0 (R/W): Right justify
All the A/D conversion result registers change their data alignment immediately after this bit is al-
tered. This does not affect the conversion results.
Left justified (ADC12A_nTRG.STMD bit = 1)
Right justified (ADC12A_nTRG.STMD bit = 0) 0
Bit 6
CNVMD
This bit sets the A/D conversion mode.
1 (R/W): Continuous conversion mode
0 (R/W): One-time conversion mode
19-8
Bit name
Initial
0x0
0x0
0x0
STMD
0
CNVMD
0
0x0
–
0
0x7
15
14
(MSB)
0
Figure 19.7.1 Conversion Data Alignment
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
–
R
H0
R/W
ADC12A_nADD.ADD[15:0] bits
13
12
11
10
9
8
12-bit conversion result
0
0
(MSB)
12-bit conversion result
S1C31D50/D51 TECHNICAL MANUAL
Remarks
7
6
5
4
3
2
1
(LSB) 0
0
0
(Rev. 2.00)
0
0
(LSB)
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