Interrupts; Control Registers; Pwga Control Register - Epson S1C31D50 Technical Manual

Cmos 32-bit single chip
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2.5 Interrupts

CLG has a function to generate the interrupts shown in Table 2.5.1.
Interrupt
IOSC oscillation stabiliza-
tion waiting completion
OSC1 oscillation stabili-
zation waiting completion
OSC3 oscillation stabili-
zation waiting completion
OSC1 oscillation stop
OSC3 oscillation auto-
trimming completion
OSC3 oscillation auto-
trimming error
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the CPU
core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more
information on interrupt control, refer to the "Interrupt" chapter.

2.6 Control Registers

PWGA Control Register

Register name
Bit
PWGACTL
15–8 –
7–6 –
5
4
3–2 –
1–0 REGMODE[1:0]
Bits 15–6 Reserved
Bit 5
REGDIS
This bit enables the V
1 (R/WP): Enable
0 (R/WP): Disable
Bit 4
REGSEL
This bit controls the V
1 (R/WP): mode0
0 (R/WP): mode1
Bits 3–2
Reserved
Bits 1–0
REGMODE[1:0]
These bits control the V
PWGACTL.REGMODE[1:0] bits
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 2.5.1 CLG Interrupt Functions
Interrupt flag
CLGINTF.IOSCSTAIF
When the IOSC oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STAIF When the OSC1 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC3STAIF When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STPIF When OSC1CLK is stopped, or when the CLGOSC.
OSC1EN or CLGOSC1.OSDEN bit setting is al-
tered from 1 to 0.
CLGINTF.OSC3TEDIF When the OSC3 oscillation auto-trimming opera-
tion has completed
CLGINTF.OSC3TERIF When the OSC3 oscillation auto-trimming opera-
tion has terminated due to an error
Bit name
Initial
0x00
0x0
REGDIS
REGSEL
0x0
0x0
regulator discharge function.
D1
regulator voltage mode.
D1
regulator operating mode.
D1
Table 2.6.1 Internal Regulator Operating Mode
0x3
0x2
0x1
0x0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Set condition
Reset
R/W
R
R
0
H0
R/WP
1
H0
R/WP
R
H0
R/WP
Operating mode
Economy mode
Normal mode
Reserved
Automatic mode
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Remarks
2-15

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