Rfc Ch.n Interrupt Flag Register; Rfc Ch.n Interrupt Enable Register - Epson S1C31D50 Technical Manual

RFC Ch.n Interrupt Flag Register

Register name Bit
RFC_nINTF 15–8 –
7–5 –
4
3
2
1
0
Bits 15–5 Reserved
Bit 4 OVTCIF
Bit 3 OVMCIF
Bit 2 ESENBIF
Bit 1 ESENAIF
Bit 0 EREFIF
These bits indicate the RFC interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
The following shows the correspondence between the bit and interrupt:
RFC_nINTF.OVTCIF bit: Time base counter overflow error interrupt
RFC_nINTF.OVMCIF bit: Measurement counter overflow error interrupt
RFC_nINTF.ESENBIF bit: Sensor B oscillation completion interrupt
RFC_nINTF.ESENAIF bit: Sensor A oscillation completion interrupt
RFC_nINTF.EREFIF bit: Reference oscillation completion interrupt

RFC Ch.n Interrupt Enable Register

Register name Bit
RFC_nINTE 15–8 –
7–5 –
4
3
2
1
0
Bits 15–5 Reserved
Bit 4 OVTCIE
Bit 3 OVMCIE
Bit 2 ESENBIE
Bit 1 ESENAIE
Bit 0 EREFIE
These bits enable RFC interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
RFC_nINTE.OVTCIE bit: Time base counter overflow error interrupt
RFC_nINTE.OVMCIE bit: Measurement counter overflow error interrupt
RFC_nINTE.ESENBIE bit: Sensor B oscillation completion interrupt
RFC_nINTE.ESENAIE bit: Sensor A oscillation completion interrupt
RFC_nINTE.EREFIE bit: Reference oscillation completion interrupt
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x0
OVTCIF 0
OVMCIF 0
ESENBIF 0
ESENAIF 0
EREFIF 0
Bit name Initial
0x00
0x0
OVTCIE 0
OVMCIE 0
ESENBIE 0
ESENAIE 0
EREFIE 0
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
20 R/F CONVERTER (RFC)
Remarks
Remarks
20-11