Table of Contents
Advertisement
Writing 1 to this bit executes 30-second correction and an enabled interrupt occurs even if the RT-
CACTLL.RTCRUN bit = 0. The correction takes up to 2/256 seconds. The RTCACTLL.RTCADJ bit
is automatically cleared to 0 when the correction has finished. For more information on the 30-second
correction, refer to "Real-Time Clock Counter Operations."
Notes: • Be sure to avoid writing to this bit when the RTCACTLL.RTCBSY bit = 1.
• Do not write 1 to this bit again while the RTCACTLL.RTCADJ bit = 1.
Bit 1
RTCRST
This bit resets the 1 Hz counter, the RTCACTLL.RTCADJ bit, and the RTCACTLL.RTCHLD bit.
1 (W):
Reset
0 (W):
Ineffective
1 (R):
Reset is being executed.
0 (R):
Reset has finished. (Normal operation)
This bit is automatically cleared to 0 after reset has finished.
Bit 0
RTCRUN
This bit starts/stops the real-time clock counter.
1 (R/W): Running/start control
0 (R/W): Idle/stop control
When the real-time clock counter stops counting by writing 0 to this bit, the counter retains the value
when it stopped. Writing 1 to this bit again resumes counting from the value retained.
RTCA Control Register (High Byte)
Register name
Bit
RTCACTLH
7
6–0 RTCTRM[6:0]
Bit 7
RTCTRMBSY
This bit indicates whether the theoretical regulation is currently executed or not.
1 (R):
Theoretical regulation is executing.
0 (R):
Theoretical regulation has finished (or not executed).
This bit goes 1 when a value is written to the RTCACTLH.RTCTRM[6:0] bits. The theoretical regula-
tion takes up to 1 second for execution. This bit reverts to 0 automatically after the theoretical regula-
tion has finished execution.
Bits 6–0
RTCTRM[6:0]
Write the correction value for adjusting the 1 Hz frequency to these bits to execute theoretical regula-
tion. For a calculation method of correction value, refer to "Theoretical Regulation Function."
Notes: • When the RTCACTLH.RTCTRMBSY bit = 1, the RTCACTLH.RTCTRM[6:0] bits cannot be
rewritten.
• Writing 0x00 to the RTCACTLH.RTCTRM[6:0] bits sets the RTCACTLH.RTCTRMBSY bit to
1 as well. However, no correcting operation is performed.
RTCA Second Alarm Register
Register name
Bit
RTCAALM1
15
14–12 RTCSHA[2:0]
11–8 RTCSLA[3:0]
7–0 –
Bit 15
Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
RTCTRMBSY
0
0x00
Bit name
Initial
–
0
0x0
0x0
0x00
Seiko Epson Corporation
10 REAL-TIME CLOCK (RTCA)
Reset
R/W
H0
R
–
H0
W
Read as 0x00.
Reset
R/W
–
R
–
H0
R/W
H0
R/W
–
R
Remarks
Remarks
10-7
Advertisement
Table of Contents
