Division Mode; Execution Cycle - Epson S1C63003 Technical Manual

18 inTeGeR MulTiPlieR
18.4

Division Mode

To perform a division, set the divisor to the source register (SR) and the dividend to the destination register (DRH
and DRL), then write "1" to the calculation mode select register (CALMD). The division takes 10 CPU clock cycles
from writing "1" to CALMD until the quotient is loaded into the low-order 8 bits (DRL) of the destination register
and the remainder is loaded into the high-order 8 bits (DRH) of the destination register. At the same time the result is
loaded, the operation flags (NF, VF and ZF) are updated. However, when an overflow results (if the quotient exceeds
the 8-bit range), the destination register (DRH and DRL) does not change its contents as it maintains the dividend.
The following shows the conditions that change the operation flag states and examples of division.
N flag: Set when the MSB of DRL is "1" and reset when it is "0."
V flag: Set when the quotient exceeds the 8-bit range and reset when it is within the 8-bit range.
Z flag: Set when the 8-bit value in DRL is 00H and reset when it is not 00H.
<examples of division>
DRH/DRL (dividend) SR (divisor) DRL (quotient) DRH (remainder)
1A16H
332CH
0000H
2468H
In the example of "2468H" ÷ "13H" shown above, DRH/DRL maintains the dividend because the quotient overflows
the 8-bit. To get the correct results when an overflow has occurred, perform the division with two steps as shown
below.
1. Divide the high-order 8 bits of the dividend (24H) by the divisor (13H) and then store the quotient (01H) to
memory.
DRH/DRL (dividend) SR (divisor) DRL (quotient) DRH (remainder)
0024H
2. Keep the remainder (11H) in DRH and load the low-order 8 bits of the dividend (68H) to DRL, then perform
division again.
DRH/DRL (dividend) SR (divisor) DRL (quotient) DRH (remainder)
1168H
The correct result is obtained as the quotient = 01EAH (the first and second results of DRL are merged into 16 bits)
and the remainder = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they cannot
indicate the states according to the final operation results.
Note: Make sure that the division results are correct using software as the hardware does not check.
18.5

execution Cycle

Both the multiplication and division take 10 CPU clock cycles for an operation. Therefore, before the results can be
read from the destination register DRH/DRL, wait at least 5 bus cycles after writing to CALMD. The same applies
to reading the operation flags NF/VF/ZF. The following shows a sample program.
ldb %ext, src_data@h
ldb %xl, src_data@l
ldb %ext, au@h
ldb %yl, au@l
;
ldb %ba, [%x]+
ldb [%y]+, %ba
ldb %ba, [%x]+
ldb [%y]+, %ba
ldb %ba, [%x]+
ldb [%y]+, %ba
;
ld [%y], 0b0001
;
18-2
64H 42H
64H 83H
58H 00H
13H 68H
13H 01H
13H EAH
; Set RAM address for operand
; Set multiplier I/O memory address
; Set data to SR
; Set data to DRL
; Set data to DRH
; Start operation (select division mode)
Seiko epson Corporation
NF
4EH 0
00H 1
00H 0
24H 1
NF
11H 0
NF
0AH 1
S1C63003/004/008/016 TeChniCal Manual
VF ZF
0 0
0 0
0 1
1 0
VF ZF
0 0
VF ZF
0 0
(Rev. 1.1)