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11 SUPPLY VOLTAGE DETECTOR (SVD3)
Bit 0
SVDIF
This bit indicates the low power supply voltage detection interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
Note: The SVD3 internal circuit is initialized if the interrupt flag is cleared while SVD3 is in operation
after 1 is written to the SVD3CTL.MODEN bit.
SVD3 Interrupt Enable Register
Register name
Bit
SVD3INTE
15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0
SVDIE
This bit enables low power supply voltage detection interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Notes: • If the SVD3CTL.SVDRE[3:0] bits are set to 0xa, no low power supply voltage detection
interrupt will occur, as a reset is issued at the same timing as an interrupt.
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be
cleared before enabling interrupts.
11-8
Bit name
Initial
0x00
0x00
SVDIE
0
Seiko Epson Corporation
Reset
R/W
–
R
–
–
R
H0
R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
(Rev. 2.00)
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