Qspi Ch.n Control Register - Epson S1C31D50 Technical Manual

Bit 0 MST
This bit sets the QSPI operating mode (master mode or slave mode).
1 (R/W): Master mode
0 (R/W): Slave mode
Note: The QSPI_nMOD register settings can be altered only when the QSPI_nCTL.MODEN bit = 0.

QSPI Ch.n Control Register

Register name Bit
QSPI_nCTL 15–8 –
7–4 –
3
2
1
0
Bits 15–4 Reserved
Bit 3 DIR
This bit sets the data transfer direction on the QSDIOn[3:0] lines when the QSPI_nMOD.TMOD[1:0]
bits are set to 1 or 2.
1 (R/W): Input
0 (R/W): Output
Bit 2 MSTSSO
This bit controls and indicates the #QSPISSn pin status.
1 (R/W): #QSPISSn = high (The device is deselected.)
0 (R/W): #QSPISSn = low (The device is selected.)
In memory mapped access mode, the #QSPISSn pin is automatically controlled by the internal state
machine. Reading this bit allows monitoring of the current #QSPISSn pin output status at any time.
Bit 1 SFTRST
This bit issues software reset to QSPI.
1 (W): Issue software reset
0 (W): Ineffective
1 (R): Software reset is executing.
0 (R): Software reset has finished. (During normal operation)
Setting this bit resets the QSPI shift register and transfer bit counter. This bit is automatically cleared
after the reset processing has finished.
Bit 0 MODEN
This bit enables the QSPI operations.
1 (R/W): Enable QSPI operations (The operating clock is supplied.)
0 (R/W): Disable QSPI operations (The operating clock is stopped.)
Note: If the QSPI_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data being
sent/received cannot be guaranteed. When setting the QSPI_nCTL.MODEN bit to 1 again after
that, be sure to write 1 to the QSPI_nCTL.SFTRST bit as well.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x0
DIR 0
MSTSSO 1
SFTRST 0
MODEN 0
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
Remarks
15-31