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Bit 2
TXSTART
This bit issues a START condition in master mode. This bit is ineffective in slave mode.
1 (W):
Issue a START condition.
0 (W):
Ineffective
1 (R):
On standby or during generating a START condition
0 (R):
START condition has been generated.
This bit is automatically cleared when a START condition has been generated.
Bit 1
SFTRST
This bit issues software reset to the I2C.
1 (W):
Issue software reset
0 (W):
Ineffective
1 (R):
Software reset is executing.
0 (R):
Software reset has finished. (During normal operation)
Setting this bit resets the I2C transmit/receive control circuit and interrupt flags. This bit is automati-
cally cleared after the reset processing has finished.
Bit 0
MODEN
This bit enables the I2C operations.
1 (R/W): Enable I2C operations (The operating clock is supplied.)
0 (R/W): Disable I2C operations (The operating clock is stopped.)
Note: If the I2C_nCTL.MODEN bit is altered from 1 to 0 while sending/receiving data, the data
being sent/received cannot be guaranteed. When setting the I2C_nCTL.MODEN bit to 1
again after that, be sure to write 1 to the I2C_nCTL.SFTRST bit as well.
I2C Ch.n Transmit Data Register
Register name
Bit
I2C_nTXD
15–8 –
7–0 TXD[7:0]
Bits 15–8 Reserved
Bits 7–0
TXD[7:0]
Data can be written to the transmit data buffer through these bits. Make sure the I2C_nINTF.TBEIF
bit is set to 1 before writing data.
Note: Be sure to avoid writing to the I2C_nTXD register when the I2C_nINTF.TBEIF bit = 0, otherwise
transmit data cannot be guaranteed.
I2C Ch.n Receive Data Register
Register name
Bit
I2C_nRXD
15–8 –
7–0 RXD[7:0]
Bits 15–8 Reserved
Bits 7–0
RXD[7:0]
The receive data buffer can be read through these bits.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R
2
16 I
C (I2C)
Remarks
Remarks
16-21
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