Input/Output Pins; Clock Sources - Epson S1C31D50 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
CLG
OSC1
X'tal1
OSC2
OSC3
X'tal3/ OSC4
Ceramic3
EXOSCEN
EXOSC
clock input
FOUT
FOUTDIV[2:0]

2.3.2 Input/Output Pins

Table 2.3.2.1 lists the CLG pins.
Pin name I/O*
OSC1 A
OSC2 A
OSC3 A
OSC4 A
EXOSC I
FOUT O
If the port is shared with the CLG input/output function and other functions, the CLG function must be assigned to
the port. For more information, refer to the "I/O Ports" chapter.

2.3.3 Clock Sources

IOSC oscillator circuit
The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1
shows the configuration of the IOSC oscillator circuit.
2-6
IOSCEN
IOSC
IOSCCLK
oscillator Divider
circuit
OSC1EN
OSC1
OSC1CLK
oscillator Divider
circuit
OSC3EN
OSC3
OSC3CLK
oscillator Divider
circuit
EXOSC
EXOSCCLK
circuit
FOUTEN
FOUT
output
circuit
Figure 2.3.1.1 CLG Configuration
Table 2.3.2.1 List of CLG Pins
Initial status*
– OSC1 oscillator circuit input
– OSC1 oscillator circuit output
– OSC3 oscillator circuit input
– OSC3 oscillator circuit output
I EXOSC clock input
O (L) FOUT clock output
Seiko Epson Corporation
CLKSRC[1:0]
CLKDIV[1:0]
WUPSRC[1:0]
WUPDIV[1:0]
WUPMD
System
Clock
clock
selector
controller
SLEEP, WAKE-UP
Clock
selector
Clock
selector
Function
* Indicates the status when the pin is configured for CLG.
S1C31D50/D51 TECHNICAL MANUAL
SYSCLK
To CPU and bus
Peripheral circuit 1
CLKSRC[x:0]
CLKDIV[x:0]
Peripheral circuit n
CLKSRC[x:0]
CLKDIV[x:0]
(Rev. 2.00)