Clg Osc3 Control Register - Epson S1C31D50 Technical Manual

For more information, refer to "OSC1 oscillator circuit characteristics, Internal gate capacitance C
in the "Electrical Characteristics" chapter.
Bits 7–6 INV1B[1:0]
These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 oscillator
circuit.
Table 2.6.6 Setting Oscillation Inverter Gain at OSC1 Boost Startup
Note: The CLGOSC1.INV1B[1:0] bits must be set to a value equal to or larger than the CLGOSC1.
INV1N[1:0] bits.
Bits 5–4 INV1N[1:0]
These bits set the oscillation inverter gain applied at normal operation of the OSC1 oscillator circuit.
Table 2.6.7 Setting Oscillation Inverter Gain at OSC1 Normal Operation
Bits 3–2 Reserved
Bits 1–0 OSC1WT[1:0]
These bits set the oscillation stabilization waiting time for the OSC1 oscillator circuit.

CLG OSC3 Control Register

Register name Bit
CLGOSC3 15–12 –
11–10 OSC3FQ[1:0]
9
8
7–6 –
5–4 OSC3INV[1:0]
3
2–0 OSC3WT[2:0]
Bits 15–12 Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 2.6.5 OSC1 Internal Gate Capacitance Setting
CLGOSC1.CGI1[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLGOSC1.INV1B[1:0] bits
0x3
0x2
0x1
0x0
CLGOSC1.INV1N[1:0] bits
0x3
0x2
0x1
0x0
Table 2.6.8 OSC1 Oscillation Stabilization Waiting Time Setting
CLGOSC1.OSC1WT[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x0
0x1
OSC3MD
–
0x0
0x3
OSC3STM
0x6
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Capacitance
Max.
↑
↓
Min.
Inverter gain
Max.
↑
↓
Min.
Inverter gain
Max.
↑
↓
Min.
Oscillation stabilization waiting time
65,536 clocks
16,384 clocks
4,096 clocks
Reserved
Reset R/W
– R –
H0 R/WP
0 H0 R/WP
0 – R
– R
H0 R/WP
0 H0 R/WP
H0 R/WP
"
GI1
Remarks
2-19