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4 Memory and Bus
4.1 Overview
This IC supports up to 16M bytes of accessible memory space for both instructions and data.
The features are listed below.
• Embedded Flash memory that supports on-board programming
• All memory and control registers are accessible in 16-bit width and one cycle.
• Write-protect function to protect system control registers
Figure 4.1.1 shows the memory map.
4.2 Bus Access Cycle
The CPU uses the system clock for bus access operations. First, "Bus access cycle," "Device size," and "Access
size" are defined as follows:
• Bus access cycle: One system clock period = 1 cycle
• Device size:
Bit width of the memory and peripheral circuits that can be accessed in one cycle
• Access size:
Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer)
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8-bit, 16-bit, or 32-bit instruction.
S1C17W12/W13 TECHNICAL MANUAL
(Rev. 1.2)
0xff ffff
Reserved for core I/O area (1K bytes)
(Device size: 32 bits)
0xff fc00
0xff fbff
0x01 4000
0x01 3fff
(Device size: 16 bits)
0x00 8000
0x00 7fff
0x00 7800
0x00 77ff
Display data RAM area (26 bytes)
(Device size: 16 bits)
0x00 7000
0x00 6fff
0x00 6000
0x00 5fff
Peripheral circuit area
(Device size: 16 bits)
0x00 4000
0x00 3fff
0x00 0800
0x00 07ff
Debug RAM area (64 bytes)
0x00 07c0
0x00 07bf
(Device size: 32 bits)
0x00 0000
Figure 4.1.1 Memory Map
Seiko Epson Corporation
Reserved
Flash area
(48K bytes)
Reserved
Reserved
(8K bytes)
Reserved
RAM area
(2K bytes)
4 MEMORY AND BUS
4-1
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