Data Format; Operations; Initialization - Epson S1C31D50 Technical Manual

14.4 Data Format

The SPIA data length can be selected from 2 bits to 16 bits by setting the SPIA_nMOD.CHLN[3:0] bits. The input/
output permutation is configurable to MSB first or LSB first using the SPIA_nMOD.LSBFST bit. Figure 14.4.1
shows a data format example when the SPIA_nMOD.CHLN[3:0] bits = 0x7, the SPIA_nMOD.CPOL bit = 0 and
the SPIA_nMOD.CPHA bit = 0.
Cycle No.
SPIA_nMOD. SPICLKn
LSBFST bit
SDOn
0
SDIn
SDOn
1
SDIn
Writing Dw[7:0] to the SPIA_nTXD register
Figure 14.4.1 Data Format Selection Using the SPIA_nMOD.LSBFST Bit
(SPIA_nMOD.CHLN[3:0] bits = 0x7, SPIA_nMOD.CPOL bit = 0, SPIA_nMOD.CPHA bit = 0)

14.5 Operations

14.5.1 Initialization

SPIA Ch.n should be initialized with the procedure shown below.
1. <Master mode only> Generate a clock by controlling the 16-bit timer and supply it to SPIA Ch.n.
2. Configure the following SPIA_nMOD register bits:
- SPIA_nMOD.PUEN bit
- SPIA_nMOD.NOCLKDIV bit
- SPIA_nMOD.LSBFST bit
- SPIA_nMOD.CPHA bit
- SPIA_nMOD.CPOL bit
- SPIA_nMOD.MST bit
3. Assign the SPIA Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
4. Set the following SPIA_nCTL register bits:
- Set the SPIA_nCTL.SFTRST bit to 1. (Execute software reset)
- Set the SPIA_nCTL.MODEN bit to 1. (Enable SPIA Ch.n operations)
5. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the SPIA_nINTF register.
- Set the interrupt enable bits in the SPIA_nINTE register to 1. *
* The initial value of the SPIA_nINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the
SPIA_nINTE.TBEIE bit is set to 1.
6. Configure the DMA controller and set the following SPIA control bits when using DMA transfer:
- Write 1 to the DMA transfer request enable bits
in the SPIA_nTBEDMAEN and SPIA_nRBFDMAEN registers. (Enable DMA transfer requests)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
1 2 3
Dw7 Dw6 Dw5
Dr7 Dr6 Dr5
Dw0 Dw1 Dw2
Dr0 Dr1 Dr2
(Enable input pin pull-up/down)
(Select master mode operating clock)
(Select MSB first/LSB first)
(Select clock phase)
(Select clock polarity)
(Select master/slave mode)
Seiko Epson Corporation
14 SYNCHRONOUS SERIAL INTERFACE (SPIA)
4 5 6
Dw4 Dw3 Dw2
Dr4 Dr3 Dr2
Dw3 Dw4 Dw5
Dr3 Dr4 Dr5
Loading Dr[7:0] to the SPIA_nRXD register
(Clear interrupt flags)
(Enable interrupts)
7 8
Dw1 Dw0
Dr1 Dr0
Dw6 Dw7
Dr6 Dr7
14-5