Epson S1C31D50 Technical Manual page 116

Cmos 32-bit single chip
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7 I/O PORTS (PPORT)
Register name
Bit
PDIOEN
15–14 –
(Pd Port Enable
13
Register)
12
11
10
9
8
7–6 –
5
4
3
2
1
0
PDRCTL
15–14 –
(Pd Port Pull-up/down
13
Control Register)
12
11
10
9
8
7–6 –
5
4
3
2
1
0
PPORTPDINTF
15–0 –
PPORTPDINTCTL
PPORTPDCHATEN
PDMODSEL
15–8 –
(Pd Port Mode Select
7–6 –
Register)
5
4
3
2
1
0
PDFNCSEL
15–12 –
(Pd Port Function
11–10 PD5MUX[1:0]
Select Register)
9–8 PD4MUX[1:0]
7–6 PD3MUX[1:0]
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PDSELy = 0
Port
PDyMUX = 0x0
name
GPIO
(Function 0)
Peripheral
Pd0
Pd0
CPU core
Pd1
Pd1
CPU core
Pd2
Pd2
Pd3
Pd3
Pd4
Pd4
Pd5
Pd5
7-38
Bit name
Initial
0x0
PDIEN5
0
PDIEN4
0
PDIEN3
0
PDIEN2
0
PDIEN1
0
PDIEN0
0
0x0
PDOEN5
0
PDOEN4
0
PDOEN3
0
PDOEN2
0
PDOEN1
0
PDOEN0
0
0x0
PDPDPU5
0
PDPDPU4
0
PDPDPU3
0
PDPDPU2
0
PDPDPU1
0
PDPDPU0
0
0x0
PDREN5
0
PDREN4
0
PDREN3
0
PDREN2
0
PDREN1
0
PDREN0
0
0x0000
0x00
0x0
PDSEL5
0
PDSEL4
0
PDSEL3
0
PDSEL2
0
PDSEL1
1
PDSEL0
1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 7.7.12.2 Pd Port Group Function Assignment
PDyMUX = 0x1
(Function 1)
Pin
Peripheral
SWCLK
SWD
Seiko Epson Corporation
Reset
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
R
R
R
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
PDSELy = 1
PDyMUX = 0x2
(Function 2)
Pin
Peripheral
Pin
CLG
OSC3
CLG
OSC4
48
64
Remarks
pin
pin
PDyMUX = 0x3
48
64
(Function 3)
pin
pin
Peripheral
Pin
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
80
100
pin
pin
80
100
pin
pin

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