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Appendix C Mounting Precautions
This section describes various precautions for circuit board design and IC mounting.
OSC1/OSC3 oscillator circuit
• Oscillation characteristics depend on factors such as components used (resonator, C
patterns. In particular, with crystal resonators, select the appropriate capacitors (C
evaluating components actually mounted on the circuit board.
• Oscillator clock disturbances caused by noise may cause malfunctions. To prevent such disturbances, con-
sider the following points.
(1) Components such as a resonator, resistors, and capacitors connected to the OSC1 (OSC3) and OSC2 (OSC4)
pins should have the shortest connections possible.
(2) Wherever possible, avoid locating digital signal lines within 3 mm of the OSC1 (OSC3) and OSC2 (OSC4)
pins or related circuit components and wiring. Rapidly-switching signals, in particular, should be kept at a
distance from these components. Since the spacing between layers of multi-layer printed circuit boards is
a mere 0.1 mm to 0.2 mm, the above precautions also apply when positioning digital signal lines on other
layers.
Never place digital signal lines alongside such components or wiring, even if more than 3 mm distance or
located on other layers. Avoid crossing wires.
(3) Use V
to shield the OSC1 (OSC3) and OSC2 (OSC4) pins and related
SS
wiring (including wiring for adjacent circuit board layers). Layers wired
should be adequately shielded as shown to the right. Fully ground adja-
cent layers, where possible. At minimum, shield the area at least 5 mm
around the above pins and wiring.
Even after implementing these precautions, avoid configuring digital
signal lines in parallel, as described in (2) above. Avoid crossing even
on discrete layers, except for lines carrying signals with low switching
frequencies.
(4) After implementing these precautions, check the FOUT pin output clock waveform by running the actual
application program within the product.
For the OSC1 waveform, enlarge the areas before and after the clock rising and falling edges and take spe-
cial care to confirm that the regions approximately 100 ns to either side are free of clock or spiking noise.
For the OSC3 waveform, confirm that the frequency is as designed, is free of noise, and has minimal jitter.
Failure to observe precautions (1) to (3) adequately may lead to noise in OSC1CLK and jitter in OSC3CLK.
Noise in the OSC1CLK will destabilize timers that use OSC1CLK as well as CPU Core operations. Jitter in
the OSC3 output will reduce operating frequencies.
#RESET pin
Components such as a switch and resistor connected to the #RESET pin should have the shortest connections
possible to prevent noise-induced resets.
V
pin
PP
Connect a capacitor C
fluctuations within V
PP
pin as possible and use a sufficiently thick wiring pattern that allows current
of several tens of mA to flow.
Power supply circuit
Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues.
(1) Connections from the power supply to the V
est patterns possible.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
between the V
and V
VPP
SS
± 1 V. The C
should be placed as close to the V
VPP
DD
Seiko Epson Corporation
APPENDIX C MOUNTING PRECAUTIONS
pins to suppress
PP
PP
and V
pins should be implemented via the shortest, thick-
SS
, C
) and circuit board
G
D
, C
) only after fully
G
D
Sample V
pattern (OSC1)
SS
OSC1
OSC2
V
SS
V
pin connection example
PP
Pin
Pin
V
PP
V
SS
C
C
VPP
VPP
AP-C-1
V
PP
V
SS
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