Data Transmission In Master Mode - Epson S1C31D50 Technical Manual

15 Quad Synchronous Serial Interface (QSPI)
- QSPI_nMMACFG2.DUMDL[3:0] bits
- QSPI_nMMACFG2.DUMLN[3:0] bits
- QSPI_nMMACFG2.DATTMOD[1:0] bits (Select data cycle transfer mode)
- QSPI_nMMACFG2.DUMTMOD[1:0] bits (Select dummy cycle transfer mode)
- QSPI_nMMACFG2.ADRTMOD[1:0] bits (Select address cycle transfer mode)
- QSPI_nMMACFG2.ADRCYC bit
- QSPI_nMB.XIPACT[7:0] bits
- QSPI_nMB.XIPEXT[7:0] bits
4. Assign the QSPI Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
5. Set the following QSPI_nCTL register bits:
- Set the QSPI_nCTL.SFTRST bit to 1.
- Set the QSPI_nCTL.MODEN bit to 1.
6. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the QSPI_nINTF register.
- Set the interrupt enable bits in the QSPI_nINTE register to 1. * (Enable interrupts)
* The initial value of the QSPI_nINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the
QSPI_nINTE.TBEIE bit is set to 1.
7. Configure the DMA controller and set the following QSPI control bits when using DMA transfer:
- Write 1 to the DMA transfer request enable bits in the QSPI_nTBEDMAEN, QSPI_nRBFDMAEN,
and QSPI_nFRLDMAEN registers.

15.5.4 Data Transmission in Master Mode

A data sending procedure and operations in master mode are shown below. Figures 15.5.4.1 and 15.5.4.2 show a
timing chart and a flowchart, respectively.
Data sending procedure
1. Set the QSPI_nCTL.DIR bit to 0 when QSPI Ch.n is set to dual or quad transfer mode. (This setting is not
necessary in single transfer mode.)
2. Assert the slave select signal for the external slave device to be accessed by controlling the QSPI_nCTL.
MSTSSO bit or the general-purpose output port used for an extra slave select signal output (if necessary).
3. Check to see if the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
4. Write transmit data to the QSPI_nTXD register.
5. Wait for a QSPI interrupt when using interrupt.
6. Repeat Steps 3 to 5 (or 3 and 4) until the end of transmit data.
7. Negate the slave select signal that has been asserted in Step 2 by controlling the QSPI_nCTL.MSTSSO bit
or the general-purpose output port (if necessary).
Data sending operations
QSPI Ch.n starts data sending operations when transmit data is written into the QSPI_nTXD register.
The transmit data in the QSPI_nTXD register is automatically transferred to the shift register and the QSPI_
nINTF.TBEIF bit is set to 1. If the QSPI_nINTE.TBEIE bit = 1 (transmit buffer empty interrupt enabled), a
transmit buffer empty interrupt occurs at the same time.
The QSPICLKn pin outputs clocks for the number of cycles specified by the QSPI_nMOD.CHLN[3:0] bits and
the transmit data bits are output in sequence from the QSDIOn pins, according to the transfer mode specified by
the QSPI_nMOD.TMOD[1:0] bits, in sync with these clocks.
Even if the clock is being output from the QSPICLKn pin, the next transmit data can be written to the QSPI_
nTXD register after making sure the QSPI_nINTF.TBEIF bit is set to 1.
If transmit data has not been written to the QSPI_nTXD register after the last clock is output from the QSPI-
CLKn pin, the clock output halts and the QSPI_nINTF.TENDIF bit is set to 1. At the same time QSPI issues an
end-of-transmission interrupt request if the QSPI_nINTE.TENDIE bit = 1.
15-12
(Select dummy cycle drive length)
(Select dummy cycle length)
(Select 24 or 32-bit address cycle)
(Set XIP activation mode byte)
(Set XIP termination mode byte)
(Execute software reset)
(Enable QSPI Ch.n operations)
(Clear interrupt flags)
(Enable DMA transfer requests)
Seiko Epson Corporation
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)