Table of Contents
Advertisement
21 HW Processor (HWP) and Sound Output
SDAC Mode Register
Register name
Bit
SDACMOD
15–9 –
8
7–1 –
0
Bits 15–9 Reserved
Bit 8
PWMOUTEN
This bit enables the SDAC output pins to output the PWM signals.
1 (R/W): Enable PWM signal output
0 (R/W): Disable PWM signal output
Bits 7–1
Reserved
Bit 0
MODE
Always set this bit to 0.
SDAC Data Register
Register name
Bit
SDACDAT
15–10 –
9–0 DAT[9:0]
Bits 15–10 Reserved
Bits 9–1
DAT[9:0]
These bits store sound data.
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
SDAC Interrupt Flag Register
Register name
Bit
SDACINTF
15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1
ERRIF
Bit 0
DATREQIF
These bits indicate the SDAC interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
The following shows the correspondence between the bit and interrupt:
SDACINTF.ERRIF bit:
SDACINTF.DATREQIF bit: Data request interrupt
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
21-28
Bit name
Initial
0x00
PWMOUTEN
0
0x00
MODE
0
Bit name
Initial
0x00
0x000
Bit name
Initial
0x00
0x00
ERRIF
0
DATREQIF
0
Error occurrence interrupt
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
H0
R
H0
R/W
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
–
R
H0
R/W
Cleared by writing 1.
H0
R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 2.00)
Advertisement
Table of Contents
