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DMAC Primary-Alternate Clear Register
Register name
Bit
DMACPACLR
31–0 PACLR[31:0]
Bits 31–0 PACLR[31:0]
These bits disable the alternate data structures.
1 (W):
Disable alternate data structure (The DMACPASET register is cleared to 0.)
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Priority Set Register
Register name
Bit
DMACPRSET
31–0 PRSET[31:0]
Bits 31–0 PRSET[31:0]
These bits increase the priority of each channel.
1 (W):
Increase priority
0 (W):
Ineffective
1 (R):
Priority = High
0 (R):
Priority = Normal
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Priority Clear Register
Register name
Bit
DMACPRCLR
31–0 PRCLR[31:0]
Bits 31–0 PRCLR[31:0]
These bits decrease the priority of each channel.
1(W):
Decrease priority (The DMACPRSET register is cleared to 0.)
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Error Interrupt Flag Register
Register name
Bit
DMACERRIF
31–24 –
23–16 –
15–8 –
7–1 –
0
Bits 31–1 Reserved
Bit 0
ERRIF
This bit indicates the DMAC error interrupt cause occurrence status.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
–
Bit name
Initial
0x0000
0000
Bit name
Initial
–
Bit name
Initial
0x00
0x00
0x00
0x00
ERRIF
0
Seiko Epson Corporation
6 DMA CONTROLLER (DMAC)
Reset
R/W
–
W
–
Reset
R/W
H0
R/W
–
Reset
R/W
–
W
–
Reset
R/W
–
R
–
–
R
–
R
–
R
H0
R/W
Cleared by writing 1.
Remarks
Remarks
Remarks
Remarks
6-13
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