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6 DMA CONTROLLER (DMAC)
DMAC Request Mask Clear Register
Register name
Bit
DMACRMCLR
31–0 RMCLR[31:0]
Bits 31–0 RMCLR[31:0]
These bits cancel the mask state of DMA transfer requests from peripheral circuits
1 (W):
Cancel mask state of DMA transfer requests from peripheral circuits
(The DMACRMSET register is cleared to 0.)
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Enable Set Register
Register name
Bit
DMACENSET
31–0 ENSET[31:0]
Bits 31–0 ENSET[31:0]
These bits enable each DMAC channel.
1 (W):
Enable DMAC channel
0 (W):
Ineffective
1 (R):
Enabled
0 (R):
Disabled
These bits are cleared after the DMA transfer has completed.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Enable Clear Register
Register name
Bit
DMACENCLR
31–0 ENCLR[31:0]
Bits 31–0 ENCLR[31:0]
These bits disable each DMAC channel.
1 (W):
Disable DMAC channel (The DMACENSET register is cleared to 0.)
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Primary-Alternate Set Register
Register name
Bit
DMACPASET
31–0 PASET[31:0]
Bits 31–0 PASET[31:0]
These bits enable the alternate data structures.
1 (W):
Enable alternate data structure
0 (W):
Ineffective
1 (R):
The alternate data structure has been enabled.
0 (R):
The primary data structure has been enabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
6-12
Bit name
Initial
–
Bit name
Initial
0x0000
0000
Bit name
Initial
–
Bit name
Initial
0x0000
0000
Seiko Epson Corporation
Reset
R/W
–
W
–
Reset
R/W
H0
R/W
–
Reset
R/W
–
W
–
Reset
R/W
H0
R/W
–
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
Remarks
(Rev. 2.00)
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