Adc12A Ch.n Dma Request Enable Register M; Adc12A Ch.n Result Register - Epson S1C31D50 Technical Manual

ADC12A Ch.n DMA Request Enable Register m

Register name Bit
ADC12A_nDMAENm 15–0 ADCDMAEN[15:0]
Bits 15–0 ADCDMAEN[15:0]
These bits enable ADC12A to issue a DMA transfer request to the corresponding DMA controller
channel (Ch.0–Ch.15) when the A/D conversion for each analog input has completed.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.

ADC12A Ch.n Result Register

Register name Bit
ADC12A_nADD 15–0 ADD[15:0]
Bits 15–0 ADD[15:0]
The A/D conversion results are set to these bits.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x0000
Bit name Initial
0x0000
Seiko Epson Corporation
19 12-BIT A/D CONVERTER (ADC12A)
Reset R/W
H0 R/W –
Reset R/W
H0 R –
Remarks
Remarks
19-11