Adc12A Ch.n Configuration Register - Epson S1C31D50 Technical Manual

Bits 5–4 CNVTRG[1:0]
These bits select a trigger source to start A/D conversion.
ADC12A_nTRG.CNVTRG[1:0] bits
Bit 3 Reserved
Bits 2–0 SMPCLK[2:0]
These bits set the analog input signal sampling time.
ADC12A_nTRG.SMPCLK[2:0] bits

ADC12A Ch.n Configuration Register

Register name Bit
ADC12A_nCFG 15–8 –
7–2 –
1–0 VRANGE[1:0]
Note: Make sure that the ADC12A_nCTL.BSYSTAT bit is set to 0 before altering the ADC12A_nCFG reg-
ister.
Bits 15–2 Reserved
Bits 1–0 VRANGE[1:0]
These bits set the A/D converter operating voltage range.
ADC12A_nCFG.VRANGE[1:0] bits
Notes: • A/D conversion will not be performed if the ADC12_nCFG.VRANGE[1:0] bits = 0x0. Set
these bits to the value according to the operating voltage to perform A/D conversion.
• Be aware that ADC circuit current I
to a value other than 0x0 when the ADC12_nCTL.BSYSTAT bit = 1.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 19.7.2 Trigger Source Selection
0x3
0x2
0x1
0x0
Table 19.7.3 Sampling Time Settings
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
0x00
0x0
Table 19.7.4 A/D Converter Operating Voltage Range Setting
0x3
0x2
0x1
0x0
Seiko Epson Corporation
19 12-BIT A/D CONVERTER (ADC12A)
Trigger source
#ADTRGn pin (external trigger)
Reserved
16-bit timer Ch.k underflow
ADC12A_nCTL.ADST bit (software trigger)
Sampling time
(Number of CLK_T16_k cycles)
11 cycles
10 cycles
9 cycles
8 cycles
7 cycles
6 cycles
5 cycles
4 cycles
Reset R/W
– R –
– R
H0 R/W
A/D converter operating voltage range
1.8 to 5.5 V
3.6 to 5.5 V
4.8 to 5.5 V
Conversion disabled
flows if the ADC12_nCFG.VRANGE[1:0] bits are set
ADC
Remarks
19-9