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2 POWER SUPPLY, RESET, AND CLOCKS
2.2.2 Input Pin
Table 2.2.2.1 shows the SRC pin.
Pin name
#RESET
The #RESET pin is connected to the noise filter that removes pulses not conforming to the requirements. An inter-
nal pull-up resistor is connected to the #RESET pin, so the pin can be left open. For the #RESET pin characteris-
tics, refer to "#RESET pin characteristics" in the "Electrical Characteristics" chapter.
2.2.3 Reset Sources
The reset source refers to causes that request system initialization. The following shows the reset sources.
#RESET pin
Inputting a reset signal with a certain low level period to the #RESET pin issues a reset request.
POR and BOR
POR (Power On Reset) issues a reset request when the rise of V
a reset request when a certain V
system will be reset properly when the power is turned on and the supply voltage is out of the operating voltage
range. Figure 2.2.3.1 shows an example of POR and BOR internal reset operation according to variations in V
V
DD
V
SS
Internal state
X
RST
V
: Reset detection voltage V
RST-
For the POR and BOR electrical specifications, refer to "POR/BOR characteristics" in the "Electrical Charac-
teristics" chapter.
Reset request from the CPU
The CPU issues a reset request by writing 1 to the AIRCR.SYSRESETREQ bit in the system control register.
For more information, refer to the "Cortex
Watchdog timer reset
Setting the watchdog timer into reset mode will issue a reset request when the counter overflows. This helps re-
turn the runaway CPU to a normal operating state. For more information, refer to the "Watchdog timer" chapter.
Supply voltage detector reset
By enabling the low power supply voltage detection reset function, the supply voltage detector will issue a reset
request when a drop in the power supply voltage is detected. This makes it possible to put the system into reset
state if the IC must be stopped under a low voltage condition. For more information, refer to the "Supply Volt-
age Detector" chapter.
Peripheral circuit software reset
Some peripheral circuits provide a control bit for software reset (MODEN or SFTRST). Setting this bit initial-
izes the peripheral circuit control bits. Note, however, that the software reset operations depend on the periph-
eral circuit. For more information, refer to "Control Registers" in each peripheral circuit chapter.
Note: The MODEN bit of some peripheral circuits does not issue software reset.
2-4
Table 2.2.2.1 SRC Pin
I/O
Initial status
I
I (Pull-up)
voltage level is detected. Reset requests from these circuits ensure that the
DD
V
RST+
V
V
RST-
RST-
RUN
RST
Reset canceling voltage
RST+:
Figure 2.2.3.1 Example of Internal Reset by POR and BOR
-M0+ Technical Reference Manual."
®
Seiko Epson Corporation
Function
Reset input
is detected. BOR (Brown-out Reset) issues
DD
V
RST-
RUN
RST
X
Indefinite (operating limit)
X
RST
S1C31D50/D51 TECHNICAL MANUAL
DD
V
RST+
RST
RUN
X
RESET state
CPU RUN state
RUN
(Rev. 2.00)
.
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