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6 DMA CONTROLLER (DMAC)
DMAC Transfer Completion Interrupt Flag Register
Register name
Bit
DMACENDIF
31–0 ENDIF[31:0]
Bits 31–0 ENDIF[31:0]
These bits indicate the DMA transfer completion interrupt cause occurrence status of each DMAC
channel.
1 (R):
Cause of interrupt occurred
0 (R):
No cause of interrupt occurred
1 (W):
Clear flag
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Transfer Completion Interrupt Enable Set Register
Register name
Bit
DMACENDIESET
31–0 ENDIESET[31:0]
Bits 31–0 ENDIESET[31:0]
These bits enable DMA transfer completion interrupts to be generated from each DMAC channel.
1 (W):
Enable interrupt
0 (W):
Ineffective
1 (R):
Interrupt has been enabled.
0 (R):
Interrupt has been disabled.
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Transfer Completion Interrupt Enable Clear Register
Register name
Bit
DMACENDIECLR
31–0 ENDIECLR[31:0]
Bits 31–0 ENDIECLR[31:0]
These bits disable DMA transfer completion interrupts to be generated from each DMAC channel.
1 (W):
Disable interrupt (The DMACENDIESET register is cleared to 0.)
0 (W):
Ineffective
Each bit corresponds to a DMAC channel. The high-order bits for the unimplemented channels are
ineffective.
DMAC Error Interrupt Enable Set Register
Register name
Bit
DMACERRIESET
31–24 –
23–16 –
15–8 –
7–1 –
0
Bits 31–1 Reserved
6-14
Bit name
Initial
0x0000
0000
Bit name
Initial
0x0000
0000
Bit name
Initial
–
Bit name
Initial
0x00
0x00
0x00
0x00
ERRIESET
0
Seiko Epson Corporation
Reset
R/W
H0
R/W
Cleared by writing 1.
Reset
R/W
H0
R/W
–
Reset
R/W
–
W
–
Reset
R/W
–
R
–
–
R
–
R
–
R
H0
R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
Remarks
(Rev. 2.00)
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