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CONTENTS
15.5.1 Register Access Mode ........................................................................................ 15-9
15.5.2 Memory Mapped Access Mode ......................................................................... 15-10
15.5.3 Initialization ......................................................................................................... 15-11
15.5.4 Data Transmission in Master Mode .................................................................... 15-12
15.5.5 Data Reception in Register Access Master Mode ............................................. 15-14
15.5.6 Data Reception in Memory Mapped Access Mode ........................................... 15-17
15.5.7 Terminating Memory Mapped Access Operations ............................................. 15-25
15.5.8 Terminating Data Transfer in Master Mode ........................................................ 15-25
15.5.9 Data Transfer in Slave Mode .............................................................................. 15-26
15.5.10 Terminating Data Transfer in Slave Mode ......................................................... 15-27
15.6 Interrupts ..................................................................................................................... 15-27
15.7 DMA Transfer Requests .............................................................................................. 15-28
15.8 Control Registers ........................................................................................................ 15-29
QSPI Ch.n Mode Register ................................................................................................... 15-29
QSPI Ch.n Control Register ................................................................................................. 15-31
QSPI Ch.n Transmit Data Register ...................................................................................... 15-32
QSPI Ch.n Receive Data Register ....................................................................................... 15-32
QSPI Ch.n Interrupt Flag Register ....................................................................................... 15-32
QSPI Ch.n Interrupt Enable Register ................................................................................... 15-33
QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register ..................................... 15-33
QSPI Ch.n Receive Buffer Full DMA Request Enable Register ........................................... 15-34
QSPI Ch.n FIFO Data Ready DMA Request Enable Register ............................................. 15-34
QSPI Ch.n Memory Mapped Access Configuration Register 1 .......................................... 15-34
QSPI Ch.n Remapping Start Address High Register .......................................................... 15-35
QSPI Ch.n Memory Mapped Access Configuration Register 2 .......................................... 15-35
QSPI Ch.n Mode Byte Register ........................................................................................... 15-37
C (I2C) .......................................................................................................................16-1
2
16.1 Overview ...................................................................................................................... 16-1
16.2 Input/Output Pins and External Connections .............................................................. 16-2
16.2.1 List of Input/Output Pins ..................................................................................... 16-2
16.2.2 External Connections .......................................................................................... 16-2
16.3 Clock Settings .............................................................................................................. 16-3
16.3.1 I2C Operating Clock ............................................................................................ 16-3
16.3.2 Clock Supply During Debugging ......................................................................... 16-3
16.3.3 Baud Rate Generator .......................................................................................... 16-3
16.4 Operations ................................................................................................................... 16-4
16.4.1 Initialization .......................................................................................................... 16-4
16.4.2 Data Transmission in Master Mode ..................................................................... 16-5
16.4.3 Data Reception in Master Mode ......................................................................... 16-7
16.4.4 10-bit Addressing in Master Mode ..................................................................... 16-10
16.4.5 Data Transmission in Slave Mode ...................................................................... 16-11
16.4.6 Data Reception in Slave Mode ........................................................................... 16-13
16.4.7 Slave Operations in 10-bit Address Mode ......................................................... 16-15
16.4.8 Automatic Bus Clearing Operation ..................................................................... 16-15
16.4.9 Error Detection ................................................................................................... 16-16
16.5 Interrupts ..................................................................................................................... 16-17
16.6 DMA Transfer Requests .............................................................................................. 16-18
16.7 Control Registers ........................................................................................................ 16-18
I2C Ch.n Clock Control Register ......................................................................................... 16-18
I2C Ch.n Mode Register ...................................................................................................... 16-19
I2C Ch.n Baud-Rate Register .............................................................................................. 16-19
I2C Ch.n Own Address Register.......................................................................................... 16-20
I2C Ch.n Control Register ................................................................................................... 16-20
I2C Ch.n Transmit Data Register ......................................................................................... 16-21
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Seiko Epson Corporation
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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