Interrupts - Epson S1C31D50 Technical Manual

Terminating memory check
The following shows the procedure to terminate the memory check being executed.
1. Confirm that the STATE.STATE[15:0] bits = 0x0002 to 0x0005 (during memory check).
2. Confirm that the STATUS.READY bit = 1.
3. Set the COMMAND.COMMAND[7:0] bits to 0xff.
4. Write 1 to the HWPCMDTRG.HWP0TRG bit.
5. Wait until the HWPINTF.HWP0IF bit is set to 1 (interrupt).
6. Confirm that the STATE.STATE[15:0] bits = 0x0001 (mc_state_idle).
7. Write 0 to the HWPINTF.HWP0IF bit.
Memory check error
When an error occurs during processing of the memory check function, the HWPINTF.HWP1IF bit is set to 1 (an
interrupt can be generated). The error contents can be confirmed by reading the ERROR.ERROR[15:0] bits. As
shown in Table 21.4.2.2, the ERROR.ERRORx bit corresponding to the error that has occurred is set to 1.
ERROR.ERROR[15:0] bits
0000 0000 0000 0000
Non-fatal error
xxxx xxxx xxxx xxx1 (bit 0) error_command
Fatal error
x1xx xxxx xxxx xxxx (bit 14) error_function_id
1xxx xxxx xxxx xxxx (bit 15) error_others
When a non-fatal error has occurred, reissue a valid command.
When a fatal error has occurred, remove the cause of error and redo the processing from initialization.

21.5 Interrupts

The HWP has a function to generate the interrupts shown in Table 21.5.1.
Interrupt Interrupt flag
Error occurrence HWPINTF.HWP1IF When a sound play error (see Table 21.4.1.2) or a memory
State transition HWPINTF.HWP0IF When a state transition of which the interrupt has not been
Interrupt enable
To enable HWP interrupts, the HWPINTE.HWPIE bit must be set to 1. An interrupt request is sent to the CPU
core only when the interrupt flag is set in this status. For more information on interrupt control, refer to the "In-
terrupt" chapter.
State transition interrupt mask
The HWP provides a HWP internal register that contains the interrupt mask bits used for setting whether to set
the HWPINTF.HWP0IF bit (to generate an interrupt) or not when a state transition occurs. By setting the inter-
rupt mask bits to 1, an interrupt can be generated when the corresponding state transition occurs.
Function Interrupt mask bit
Sound play INTMASK.TO_MUTE
INTMASK.TO_PAUSE
INTMASK.TO_PLAY
INTMASK.TO_IDLE
Memory check INTMASK.TO_PROCESSING mc_state_idle state → mc_state_ram_rw, ram_march_c, checksum, crc state
INTMASK.TO_IDLE
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 21.4.2.2 List of Memory Check Errors
Error
error_no_error No error has occurred.
A command that is undefined or is ineffective in the cur-
rent state has been specified.
An undefined function ID has been specified.
Another error has occurred.
Table 21.5.1 HWP Interrupt Function
check error (see Table 21.4.2.2) has occurred
masked occurs
Table 21.5.2 State Transition Interrupt Mask Bits
sp_state_play state → sp_state_mute state
sp_state_play state → sp_state_pause state
sp_state_idle, mute, pause state → sp_state_play state
sp_state_init, mute, pause, play state → sp_state_idle state
mc_state_init, mc_state_ram_rw, ram_march_c, checksum, crc state → mc_state_
idle state
Seiko Epson Corporation
21 HW Processor (HWP) and Sound Output
(Command acceptable)
(Select Memory Check Stop command)
(Trigger to issue command)
(Occurrence of state transition)
(Clear interrupt flag)
Meaning
Set condition
State transition
Clear condition
Writing 0.
Writing 0.
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