Epson S1C31D50 Technical Manual page 124

Bits 9–0 CMP[9:0]
These bits set the NMI/reset generation cycle.
The value set in this register is compared with the 10-bit counter value while WDT2 is running, and
an NMI or reset is generated when they are matched.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Seiko Epson Corporation
9 WATCHDOG TIMER (WDT2)
9-5