Interrupts - Epson S1C31D50 Technical Manual

7 I/O PORTS (PPORT)
Setting output data to a GPIO port
Write data (1 = high output, 0 = low output) to be output from the Pxy pin to the PPORTPxDAT.PxOUTy bit.
Reading input data from a GPIO port
The data (1 = high input, 0 = low input) input from the Pxy pin can be read out from the PPORTPxDAT.PxINy bit.
Chattering filter function
Some ports have a chattering filter function and it can be controlled in each port. This function is enabled by
setting the PPORTPxCHATEN.PxCHATENy bit to 1. The input sampling time to remove chattering is deter-
mined by the CLK_PPORT frequency configured using the PPORTCLK register in common to all ports. The
chattering filter removes pulses with a shorter width than the input sampling time.
Input sampling time = ———————————— [second]
Make sure the Pxy port interrupt is disabled before altering the PPORTCLK register and PPORTPxCHATEN.
PxCHATENy bit settings. A Pxy port interrupt may erroneously occur if these settings are altered in an inter-
rupt enabled status. Furthermore, enable the interrupt after a lapse of four or more CLK_PPORT cycles from
enabling the chattering filter function.
If the clock generator is configured so that it will supply CLK_PPORT to PPORT in SLEEP mode, the chatter-
ing filter of the port will function even in SLEEP mode. If CLK_PPORT is configured to stop in SLEEP mode,
PPORT inactivates the chattering filter during SLEEP mode to input pin status transitions directly to itself.
Key-entry reset function
This function issues a reset request when low-level pulses are input to all the specified ports simultaneously.
Make the following settings when using this function:
1. Configure the ports to be used for key-entry reset as general-purpose input ports (refer to "Initial settings
when using a port as a general-purpose input port (only for the ports with GPIO function)").
2. Configure the input pin combination for key-entry reset using the PPORTCLK.KRSTCFG[1:0] bits.
Note: When enabling the key-entry reset function, be sure to configure the port pins to be used for it
as general-purpose input pins before setting the PPORTCLK.KRSTCFG[1:0] bits.
PPORT issues a reset request immediately after all the input pins specified by the PPORTCLK.KRSTCFG[1:0]
are set to a low level if the chattering filter function is disabled (initial status). To issue a reset request only
when low-level signals longer than the time configured are input, enable the chattering filter function for all the
ports used for key-entry reset.
The pins configured for key-entry reset can also be used as general-purpose input pins.

7.5 Interrupts

When the GPIO function is selected for the port with an interrupt function, the port input interrupt function can be
used.
Interrupt Interrupt flag
Port input PPORTPxINTF.PxIFy
interrupt
PPORTINTFGRP.PxINT Setting an interrupt flag in the port group Clearing PPORTPxINTF.PxIFy
Interrupt edge selection
Port input interrupts will occur at the falling edge of the input signal when setting the PPORTPxINTCTL.
PxEDGEy bit to 1, or the rising edge when setting to 0.
Interrupt enable
PPORT provides interrupt enable bits (PPORTPxINTCTL.PxIEy bit) corresponding to each interrupt flag. An
interrupt request is sent to the CPU core only when the interrupt flag, of which interrupt has been enabled by
the interrupt enable bit, is set. For more information on interrupt control, refer to the "Interrupt" chapter.
7-6
2 to 3
CLK_PPORT frequency [Hz]
Table 7.5.1 Port Input Interrupt Function
Rising or falling edge of the input signal
Seiko Epson Corporation
Set condition
S1C31D50/D51 TECHNICAL MANUAL
(Eq.6.2)
Clear condition
Writing 1
(Rev. 2.00)