T16 Ch.n Reload Data Register; T16 Ch.n Counter Data Register; T16 Ch.n Interrupt Flag Register - Epson S1C31D50 Technical Manual

12 16-BIT TIMERS (T16)
By writing 1 to this bit, the timer starts count operations. However, the T16_nCTL.MODEN bit must
be set to 1 in conjunction with this bit or it must be set in advance. While the timer is running, writing
0 to this bit stops count operations. When the counter stops due to a counter underflow in one-shot
mode, this bit is automatically cleared to 0.
Bits 7–2 Reserved
Bit 1 PRESET
This bit presets the reload data stored in the T16_nTR register to the counter.
1 (W): Preset
0 (W): Ineffective
1 (R): Presetting in progress
0 (R): Presetting finished or normal operation
By writing 1 to this bit, the timer presets the T16_nTR register value to the counter. However, the
T16_nCTL.MODEN bit must be set to 1 in conjunction with this bit or it must be set in advance. This
bit retains 1 during presetting and is automatically cleared to 0 after presetting has finished.
Bit 0 MODEN
This bit enables the T16 Ch.n operations.
1 (R/W): Enable (Start supplying operating clock)
0 (R/W): Disable (Stop supplying operating clock)

T16 Ch.n Reload Data Register

Register name Bit
T16_nTR 15–0 TR[15:0]
Bits 15–0 TR[15:0]
These bits are used to set the initial value to be preset to the counter.
The value set to this register will be preset to the counter when 1 is written to the T16_nCTL.PRESET
bit or when the counter underflows.
Notes: • The T16_nTR register cannot be altered while the timer is running (T16_nCTL.PRUN bit = 1),
as an incorrect initial value may be preset to the counter.
• When one-shot mode is set, the T16_nTR.TR[15:0] bits should be set to a value equal to or
greater than 0x0001.

T16 Ch.n Counter Data Register

Register name Bit
T16_nTC 15–0 TC[15:0]
Bits 15–0 TC[15:0]
The current counter value can be read out from these bits.

T16 Ch.n Interrupt Flag Register

Register name Bit
T16_nINTF 15–8 –
7–1 –
0
Bits 15–1 Reserved
Bit 0 UFIF
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
12-6
Bit name Initial
0xffff
Bit name Initial
0xffff
Bit name Initial
0x00
0x00
UFIF 0
Seiko Epson Corporation
Reset R/W
H0 R/W –
Reset R/W
H0 R –
Reset R/W
– R –
– R
H0 R/W Cleared by writing 1.
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
Remarks
(Rev. 2.00)