Epson S1C31D50 Technical Manual page 404

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 T16_5TC
04c8 (T16 Ch.5 Counter
Data Register)
0x0020 T16_5INTF
04ca
(T16 Ch.5 Interrupt
Flag Register)
0x0020 T16_5INTE
04cc (T16 Ch.5 Interrupt
Enable Register)
0x0020 04d0–0x0020 04de
Address Register name
0x0020 SPIA_2MOD
04d0 (SPIA Ch.2 Mode
Register)
0x0020 SPIA_2CTL
04d2 (SPIA Ch.2 Control
Register)
0x0020 SPIA_2TXD
04d4 (SPIA Ch.2 Transmit
Data Register)
0x0020 SPIA_2RXD
04d6 (SPIA Ch.2 Receive
Data Register)
0x0020 SPIA_2INTF
04d8 (SPIA Ch.2 Interrupt
Flag Register)
0x0020 SPIA_2INTE
04da (SPIA Ch.2 Interrupt
Enable Register)
0x0020 SPIA_2TBEDMAEN
04dc (SPIA Ch.2 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 SPIA_2RBFDMAEN
04de (SPIA Ch.2 Receive
Buffer Full DMA
Request Enable
Register)
AP-A-40
Bit Bit name
15–0 TC[15:0]
15–8 –
7–1 –
0 UFIF
15–8 –
7–1 –
0 UFIE
Bit Bit name
15–12 –
11–8 CHLN[3:0]
7–6 –
5 PUEN
4 NOCLKDIV
3 LSBFST
2 CPHA
1 CPOL
0 MST
15–8 –
7–2 –
1 SFTRST
0 MODEN
15–0 TXD[15:0]
15–0 RXD[15:0]
15–8 –
7 BSY
6–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Seiko Epson Corporation
Initial Reset R/W
0xffff H0 R
0x00 – R
0x00 – R
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
Synchronous Serial Interface (SPIA) Ch.2
Initial Reset R/W
0x0 – R
0x7 H0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x0000 H0 R/W
0x0000 H0 R
0x00 – R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
–
–
Cleared by writing 1.
–
Remarks
–
–
–
–
–
Cleared by writing 1.
Cleared by reading the
SPIA_2RXD register.
Cleared by writing to the
SPIA_2TXD register.
–
–
–
(Rev. 2.00)