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17 16-BIT PWM TIMERS (T16B)
T16B Ch.n Counter Max/Zero DMA Request Enable Register
Register name
Bit
T16B_nMZDMAEN 15–0 MZDMAEN[15:0]
Bits 15–0 MZDMAEN[15:0]
These bits enable T16B to issue a DMA transfer request to the corresponding DMA controller channel
(Ch.0–Ch.15) when the counter value reaches the MAX value or 0x0000.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
T16B Ch.n Compare/Capture m DMA Request Enable Register
Register name
Bit
T16B_nCCmDMAEN 15–0 CCmDMAEN[15:0]
Bits 15–0 CCmDMAEN[15:0]
These bits enable T16B to issue a DMA transfer request to the corresponding DMA controller channel
(Ch.0–Ch.15) when the counter value reaches the compare data or is captured.
1 (R/W): Enable DMA transfer request
0 (R/W): Disable DMA transfer request
Each bit corresponds to a DMA controller channel. The high-order bits for the unimplemented chan-
nels are ineffective.
17-32
Bit name
Initial
0x0000
Bit name
Initial
0x0000
Seiko Epson Corporation
Reset
R/W
H0
R/W
–
Reset
R/W
H0
R/W
–
S1C31D50/D51 TECHNICAL MANUAL
Remarks
Remarks
(Rev. 2.00)
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