Epson S1C31D50 Technical Manual page 200

QSPICLKn
QSDIOn[3:0]
QSPI_nINTF.TBEIF
QSPI_nINTF.RBFIF
QSPI_nINTF.TENDIF
Data (W) → QSPI_nTXD
Software operations
Figure 15.5.5.1 Example of Data Receiving Operations in Register Access Master Mode
(QSPI_nMOD.CHDL[3:0] bits = QSPI_nMOD.CHLN[3:0] bits = 0x3)
Data reception
Set the transfer direction to input
(QSPI_nCTL.DIR = 1)
(
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 0) or a general-purpose port
Read the QSPI_nINTF.TBEIF bit
QSPI_nINTF.TBEIF = 1 ?
YES
Write dummy data (or transmit data) to
the QSPI_nTXD register
Wait for an interrupt request
(QSPI_nINTF.RBFIF = 1)
Read receive data from
the QSPI_nRXD register
Receive data remained?
NO
(
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 1) or a general-purpose port
End
(A) Intermittent data reception
Figure 15.5.5.2 Data Reception Flowcharts in Register Access Master Mode
Data reception using DMA
For data reception, two DMA controller channels should be used to write dummy data to the QSPI_nTXD reg-
ister as a reception start trigger and to read the received data from the QSPI_nRXD register.
By setting the QSPI_nTBEDMAEN.TBEDMAENx
request is sent to the DMA controller and dummy data is transferred from the specified memory to the QSPI_
nTXD register via DMA Ch.x
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
1 2 3 4
Data (W) → QSPI_nTXD
QSPI_nRXD → Data (R)
1 (W) → QSPI_nINTF.TENDIF
Not necessary
Set the transfer direction to input
in single
transfer mode
) (
Assert the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 0) or a general-purpose port
Read the QSPI_nINTF.TBEIF bit
NO
Write dummy data (or transmit data) to
Wait for an interrupt request
Write dummy data (or transmit data) to
Wait for an interrupt request
YES
)
(
Negate the slave select signal output from
the #QSPISSn pin (QSPI_nCTL.MSTSSO
= 1) or a general-purpose port
(B) Continuous data reception
when the QSPI_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
1
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
1 2 3 4
Data (W) → QSPI_nTXD
Data reception
(QSPI_nCTL.DIR = 1)
QSPI_nINTF.TBEIF = 1 ?
YES
the QSPI_nTXD register
(QSPI_nINTF.TBEIF = 1)
the QSPI_nTXD register
(QSPI_nINTF.RBFIF = 1)
Read receive data from
the QSPI_nRXD register
Receive data remained?
NO
End
bit to 1 (DMA transfer request enabled), a DMA transfer
1
1 2 3 4
QSPI_nRXD → Data (R)
QSPI_nRXD → Data (R)
Not necessary
in single
transfer mode
)
NO
Execute this sequence
within the QSPICLKn
cycles equivalent to
"Data bit length - 1" from
an interrupt request
YES
)
15-15