Bits 7–0
PxIE[7:0]
These bits enable port input interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared
before enabling interrupts.
Px Port Chattering Filter Enable Register
Register name
Bit
PPORTPxCHATEN 15–8 –
7–0 PxCHATEN[7:0]
*1: The bit configuration differs depending on the port group.
Bits 15–8 Reserved
Bits 7–0
PxCHATEN[7:0]
These bits enable/disable the chattering filter function.
1 (R/W): Enable (The chattering filter is used.)
0 (R/W): Disable (The chattering filter is bypassed.)
Px Port Mode Select Register
Register name
Bit
PPORTPxMODSEL 15–8 –
7–0 PxSEL[7:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–8 Reserved
Bits 7–0
PxSEL[7:0]
These bits select whether each port is used for the GPIO function or a peripheral I/O function.
1 (R/W): Use peripheral I/O function
0 (R/W): Use GPIO function
Px Port Function Select Register
Register name
Bit
PPORTPxFNCSEL 15–14 Px7MUX[1:0]
13–12 Px6MUX[1:0]
11–10 Px5MUX[1:0]
9–8 Px4MUX[1:0]
7–6 Px3MUX[1:0]
5–4 Px2MUX[1:0]
3–2 Px1MUX[1:0]
1–0 Px0MUX[1:0]
*1: The bit configuration differs depending on the port group.
*2: The initial value may be changed by the port.
Bits 15–14 Px7MUX[1:0]
:
:
Bits 1–0
Px0MUX[1:0]
These bits select the peripheral I/O function to be assigned to each port pin.
PPORTPxFNCSEL.PxyMUX[1:0] bits
This selection takes effect when the PPORTPxMODSEL.PxSELy bit = 1.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name
Initial
0x00
0x00
Bit name
Initial
0x00
0x00
Bit name
Initial
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Table 7.6.1 Selecting Peripheral I/O Function
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
–
R
–
H0
R/W
Reset
R/W
H0
R/W
–
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
H0
R/W
Peripheral I/O function
Function 3
Function 2
Function 1
Function 0
7 I/O PORTS (PPORT)
Remarks
Remarks
Remarks
7-9