Clg Interrupt Flag Register; Clg Interrupt Enable Register - Epson S1C31D50 Technical Manual

CLG Interrupt Flag Register

Register name Bit
CLGINTF 15–9 –
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3 Reserved
Bit 8 OSC3TERIF
Bit 5 OSC1STPIF
Bit 4 OSC3TEDIF
Bit 2 OSC3STAIF
Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the interrupt as follows:
CLGINTF.OSC3TERIF bit: OSC3 oscillation auto-trimming error interrupt
CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt
CLGINTF.OSC3TEDIF bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.

CLG Interrupt Enable Register

Register name Bit
CLGINTE 15–9 –
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3 Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
OSC3TERIF 0
– 0
(reserved) 0
OSC1STPIF 0
OSC3TEDIF 0
– 0
OSC3STAIF 0
OSC1STAIF 0
IOSCSTAIF 0
Bit name Initial
0x00
OSC3TERIE 0
– 0
(reserved) 0
OSC1STPIE 0
OSC3TEDIE 0
– 0
OSC3STAIE 0
OSC1STAIE 0
IOSCSTAIE 0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
H0 R/W Cleared by writing 1.
– R –
H0 R
H0 R/W Cleared by writing 1.
H0 R/W
– R –
H0 R/W Cleared by writing 1.
H0 R/W
H0 R/W
Reset R/W
– R –
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
Remarks
Remarks
2-21