Rom Address Register; Rom Size Register; Key Code Register - Epson S1C31D50 Technical Manual

Bits 15–4 Reserved
Set to 0x000 when writing data to this register.
Bit 3 TO_MUTE
Bit 2 TO_PAUSE
Bit 1 TO_PLAY
Bit 0 TO_IDLE
These bits set whether the interrupt request when a state transition occurs during executing the sound
play function is enabled or not.
1 (W): Enable interrupt
0 (W): Mask interrupt (disabled)
For more information on the state transition interrupts that can be masked with these bits, refer to
Table 21.5.2.

ROM Address Register

Register name Bit
ROMADDR 31–0 ADDRESS[31:0]
(Sound Play)
Bits 31–0 ADDRESS[31:0]
These bits specify the sound data ROM start address.
The address should be specified with a value shown below.
In case of internal Flash:
0x00 0000, ..., 0x02 fff0 (16-byte alignment)
In case of external QSPI-Flash:
0x00 0000 + OFFSET
0x10 0000 + OFFSET
0x20 0000 + OFFSET
...
0xe0 0000 + OFFSET
0xf0 0000 + OFFSET
* The OFFSET is 0x04 0000, the start address of the memory mapped access area for external Flash
memory (refer to "Figure 4.1.1 Memory Map").

ROM Size Register

Register name Bit
ROMSIZE 31–0 SIZE[31:0]
(Sound Play)
Bits 31–0 ADDRESS[31:0]
These bits specify the sound data ROM size in bytes.
The following shows the maximum size that can be specified.
In case of internal Flash:
0x03 0000 bytes (192K bytes) or less
In case of external QSPI-Flash:
0x100 0000 bytes (16M bytes) or less

Key Code Register

Register name Bit
KEYCODE 31–0 KEYCODE[31:0]
(Sound Play)
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x0000
0000
Bit name Initial
0x0000
0000
Bit name Initial
0x0000
0000
Seiko Epson Corporation
21 HW Processor (HWP) and Sound Output
Reset R/W
H0 W –
Reset R/W
H0 W –
Reset R/W
H0 W –
Remarks
Remarks
Remarks
21-19