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13 UART (UART3)
Data transmission using DMA
By setting the UART3_nTBEDMAEN.TBEDMAENx bit to 1 (DMA transfer request enabled), a DMA trans-
fer request is sent to the DMA controller and transmit data is transferred from the specified memory to the
UART3_nTXD register via DMA Ch.x when the UART3_nINTF.TBEIF bit is set to 1 (transmit buffer empty).
This automates the data sending procedure described above.
The transfer source/destination and control data must be set for the DMA controller and the relevant DMA
channel must be enabled to start a DMA transfer in advance so that transmit data will be transferred to the
UART3_nTXD register. For more information on DMA, refer to the "DMA Controller" chapter.
Table 13.5.2.1 DMA Data Structure Configuration Example (for Data Transmission)
End pointer
Transfer source
Transfer destination UART3_nTXD register address
Control data dst_inc
dst_size
src_inc
src_size
R_power
n_minus_1
cycle_ctrl
13.5.3 Data Reception
A data receiving procedure and the UART3 Ch.n operations are shown below. Figures 13.5.3.1 and 13.5.3.2 show a
timing chart and flowcharts, respectively.
Data receiving procedure (read by one byte)
1. Wait for a UART3 interrupt when using the interrupt.
2. Check to see if the UART3_nINTF.RB1FIF bit is set to 1 (receive buffer one byte full).
3. Read the received data from the UART3_nRXD register.
4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception.
Data receiving procedure (read by two bytes)
1. Wait for a UART3 interrupt when using the interrupt.
2. Check to see if the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two bytes full).
3. Read the received data from the UART3_nRXD register twice.
4. Repeat Steps 1 to 3 (or 2 and 3) until the end of data reception.
UART3 data receiving operations
The UART3 Ch.n starts data receiving operations when a start bit is input to the USINn pin.
After the receive circuit has detected a low level as a start bit, it starts sampling the following data bits and
loads the received data into the receive shift register. The UART3_nINTF.RBSY bit is set to 1 when the start bit
is detected.
The UART3_nINTF.RBSY bit is cleared to 0 and the receive shift register data is transferred to the receive data
buffer at the stop bit receive timing.
The receive data buffer consists of a 2-byte FIFO and receives data until it becomes full. When the receive data
buffer receives the first data, it sets the UART3_nINTF.RB1FIF bit to 1 (receive buffer one byte full). If the sec-
ond data is received without reading the first data, the UART3_nINTF.RB2FIF bit is set to 1 (receive buffer two
bytes full).
13-6
Item
Memory address in which the last transmit data is stored
0x3 (no increment)
0x0 (byte)
0x0 (+1)
0x0 (byte)
0x0 (arbitrated for every transfer)
Number of transfer data
0x1 (basic transfer)
Seiko Epson Corporation
Setting example
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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