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4 MEMORY AND BUS
4.2 Bus Access Cycle
The CPU uses the system clock for bus access operations. First, "Bus access cycle," "Device size," and "Access
size" are defined as follows:
• Bus access cycle: One system clock period = 1 cycle
• Device size:
Bit width of the memory and peripheral circuits that can be accessed in one cycle
• Access size:
Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer)
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8-bit, 16-bit, or 32-bit instruction.
Note: When data is transferred to a memory in 32-bit access, the eight high-order bits are written to
the memory as 0x00 since the bit width of the S1C17 core general-purpose registers is 24 bits.
Conversely when sending from a memory to a register, the eight high-order bits are ignored.
The CPU performs 32-bit access for stack operations in an interrupt handling. In this case, the
CPU read/write 32-bit data that consists of the PSR value as the eight high-order bits and the
return address as the 24 low-order bits. For more information, refer to the "S1C17 Family S1C17
Core Manual."
The CPU adopts Harvard architecture that allows simultaneous processing of an instruction fetch and a data ac-
cess. However, they are not performed simultaneously under one of the conditions listed below. This prolongs the
instruction fetch cycle for the number of data area bus cycles.
• When the CPU executes an instruction stored in the Flash area and accesses data in the Flash area
• When the CPU executes an instruction stored in the internal RAM area and accesses data in the internal RAM
area
4.3 Flash Memory
The Flash memory is used to store application programs and data. Address 0x8000 in the Flash area is defined as
the vector table base address by default, therefore a vector table must be located beginning from this address. For
more information on the vector table, refer to "Vector Table" in the "Interrupt Controller" chapter.
4.3.1 Flash Memory Pin
Table 4.3.1.1 shows the Flash memory pin.
Pin name
V
PP
For the V
voltage, refer to "Recommended Operating Conditions, Flash programming voltage V
PP
trical Characteristics" chapter.
Note: Always leave the V
4-2
Table 4.2.1 Number of Bus Access Cycles
Device size
Access size
8 bits
16 bits
32 bits
Table 4.3.1.1 Flash Memory Pin
I/O
Initial status
P
–
pin open except when programming the Flash memory.
PP
Seiko Epson Corporation
Number of bus access
cycles
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
8 bits
16 bits
32 bits
Flash programming power supply
1
2
4
1
1
2
1
1
1
Function
" in the "Elec-
PP
S1C17W03/W04 TECHNICAL MANUAL
(Rev. 1.2)
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