Memory And Bus; Overview; Bus Access Cycle - Epson S1C17M20 Technical Manual

4 Memory and Bus

4.1 Overview

This IC supports up to 16M bytes of accessible memory space for both instructions and data.
The features are listed below.
• Embedded Flash memory that supports on-board programming
• All memory and control registers are accessible in 16-bit width and one cycle.
• Write-protect function to protect system control registers
Figure 4.1.1 shows the memory map.
0xff ffff
0xff fc00
0xff fbff
0x00 c000
0x00 bfff
0x00 8000
0x00 7fff
0x00 6000
0x00 5fff
0x00 4000
0x00 3fff
0x00 0800
0x00 07ff
0x00 07c0 Debug RAM area (64 bytes)
0x00 07bf
0x00 0000

4.2 Bus Access Cycle

The CPU uses the system clock for bus access operations. First, "Bus access cycle," "Device size," and "Access
size" are defined as follows:
• Bus access cycle: One system clock period = 1 cycle
• Device size: Bit width of the memory and peripheral circuits that can be accessed in one cycle
Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer)
• Access size:
Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can
be accessed with an 8-bit, 16-bit, or 32-bit instruction.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
S1C17M20/M21/M22
Reserved for core I/O area
(1K bytes)
(Device size: 32 bits)
Reserved
Flash area
(16K bytes)
(Device size: 16 bits)
Reserved
Peripheral circuit area
(8K bytes)
(Device size: 16 bits)
Reserved
RAM area
(2K bytes)
(Device size: 32 bits)
Figure 4.1.1 Memory Map
Seiko Epson Corporation
S1C17M23/M24/M25
0xff ffff
Reserved for core I/O area
(1K bytes)
0xff fc00
(Device size: 32 bits)
0xff fbff
Reserved
0x01 0000
0x00 ffff
Flash area
(32K bytes)
(Device size: 16 bits)
0x00 8000
0x00 7fff
Reserved
0x00 6000
0x00 5fff
Peripheral circuit area
(8K bytes)
(Device size: 16 bits)
0x00 4000
0x00 3fff
Reserved
0x00 0800
0x00 07ff
0x00 07c0 Debug RAM area (64 bytes)
0x00 07bf
RAM area
(2K bytes)
(Device size: 32 bits)
0x00 0000
4 MEMORY AND BUS
4-1