Interrupts - Epson S1C31D50 Technical Manual

18 IR REMOTE CONTROLLER (REMC3)
Example) REMC3DBCTL.TRMD bit = 0 (repeat mode), REMC3DBCTL.BUFEN bit = 1 (compare buffer enabled),
REMC3DBCTL.REMOINV bit = 0 (signal logic non-inverted)
REMC3DBCTL.PRUN
16-bit counter for
data signal generation
(DBCNT[15:0])
REMC3APLEN.APLEN[15:0]
REMC3DBLEN.DBLEN[15:0]
REMC3APLEN buffer
REMC3DBLEN buffer
REMC3INTF.APIF
Compare AP interrupt
REMC3INTF.DBIF
Compare DB interrupt
REMC3INTF.DBCNTRUN
REMC3INTF.APLENBSY
REMC3INTF.DBLENBSY
Data signal
(Modulated data)
When the compare buffer is disabled (REMC3DBCTL.BUFEN bit = 0), the 16-bit counter value is directly com-
pared with the REMC3APLEN.APLEN[15:0] and REMC3DBLEN.DBLEN[15:0] bit values. The comparison
value is altered immediately after the REMC3APLEN.APLEN[15:0] or REMC3DBLEN.DBLEN[15:0] bits are
rewritten.
When the compare buffer is enabled (REMC3DBCTL.BUFEN bit = 1), the REMC3APLEN.APLEN[15:0] and
REMC3DBLEN.DBLEN[15:0] bit values are loaded into the compare buffers provided respectively (REMC3A-
PLEN buffer and REMC3DBLEN buffer) and the 16-bit counter value is compared with the compare buffers.
The comparison values are loaded into the compare buffers when the 16-bit counter is matched with the REMC3D-
BLEN buffer (when the count for the data length has completed). Therefore, the next transmit data can be set dur-
ing the current data transmission. When the compare buffers are enabled, the buffer status flags (REMC3INTF.
APLENBSY bit and REMC3INTF.DBLENBSY bit) become effective. The flag is set to 1 when the setting value is
written to the register and cleared to 0 when the written value is transferred to the buffer.

18.5 Interrupts

The REMC3 has a function to generate the interrupts shown in Table 18.5.1.
Interrupt Interrupt flag
Compare AP REMC3INTF.APIF When the REMC3APLEN register (or
Compare DB REMC3INTF.DBIF When the REMC3DBLEN register (or
The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the
CPU core only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the "Interrupt" chapter.
18-6
0x0bd0 0x0bd1
0 1 2 3
0x0bd0
0x11b8
0x0bd0
0x11b8
16T
Figure 18.4.4.1 Continuous Data Transmission Example
Table 18.5.1 REMC3 Interrupt Function
Set condition
REMC3APLEN buffer) value and the 16-bit
counter for data signal generation are matched
REMC3DBLEN buffer) value and the 16-bit
counter for data signal generation are matched
Seiko Epson Corporation
0x11b8 0x00bd 0x00be
0 1
0x00bd
0x017a
0x00bd
0x017a
Cleared
Cleared
8T T
"0"
0x017a 0x00bd 0x00be 0x02f4
0 1
0x02f4 0x017a
0x00bd
0x02f4
Cleared Cleared
Cleared
T T 3T
"1"
Clear condition
Writing 1 to the interrupt flag or
the REMC3DBCTL.REMCRST bit
Writing 1 to the interrupt flag or
the REMC3DBCTL.REMCRST bit
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
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