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6 DMA CONTROLLER (DMAC)
6.4.3 Control Data
Set the DMA transfer information. Figure 6.4.3.1 shows the constituent elements of the control data.
31 30
29 28
27 26
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
dst_inc
dst_size
src_inc
src_size
dst_inc
Set the increment value of the transfer destination address. The setting value must be equal to or larger than the
transfer data size when the address is incremented.
dst_size
Set the size of the data to be written to the transfer destination. It should be the same value as the src_size.
src_inc
Set the increment value of the transfer source address. The setting value must be equal to or larger than the
transfer data size when the address is incremented.
src_size
Set the size of the data to be read from the transfer source. It should be the same value as the dst_size.
R_power
Set the arbitration cycle during successive data transfer.
Arbitration cycle (2
When the DMAC is performing a successive transfer, it suspends the data transfer at the cycle set with R_pow-
er. If DMA requests have been issued at that point, the DMAC re-arbitrates them according to their priorities
and then performs a DMA transfer for the channel with the highest priority.
6-4
Figure 6.4.3.1 Constituent Elements of Control Data
Table 6.4.3.1 Increment Value of Transfer Destination Address
dst_inc
0x3
0x2
0x1
0x0
Table 6.4.3.2 Size of Data Written to Transfer Destination
dst_size
0x3
0x2
0x1
0x0
Table 6.4.3.3 Increment Value of Transfer Source Address
src_inc
0x3
0x2
0x1
0x0
Table 6.4.3.4 Size of Data Read from Transfer Source
src_size
0x3
0x2
0x1
0x0
R
) = 2
R_power
Seiko Epson Corporation
R_power
n_minus_1
Increment value
No increment
+4
+2
+1
Data size
Reserved
Word
Halfword
Byte
Increment value
No increment
+4
+2
+1
Data size
Reserved
Word
Halfword
Byte
9
8
7
6
5
4
3
2
cycle_ctrl
Reserved
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
1
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