Epson S1C31D50 Technical Manual page 410

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
Address Register name
0x0020 QSPI_0INTF
0698 (QSPI Ch.0 Interrupt
Flag Register)
0x0020 QSPI_0INTE
069a (QSPI Ch.0 Interrupt
Enable Register)
0x0020 QSPI_0TBEDMAEN
069c
(QSPI Ch.0 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 QSPI_0RBFDMAEN
069e (QSPI Ch.0 Receive
Buffer Full DMA
Request Enable
Register)
0x0020 QSPI_0FRLDMAEN
06a0 (QSPI Ch.0 FIFO Data
Ready DMA Request
Enable Register)
0x0020 QSPI_0MMACFG1
06a2
(QSPI Ch.0 Memory
Mapped Access Con-
figuration Register 1)
0x0020 QSPI_0RMADRH
06a4 (QSPI Ch.0 Remap-
ping Start Address
High Register)
0x0020 QSPI_0MMACFG2
06a6 (QSPI Ch.0 Memory
Mapped Access Con-
figuration Register 2)
0x0020 QSPI_0MB
06a8 (QSPI Ch.0 Mode
Byte Register)
0x0020 06c0–0x0020 06d6
Address Register name
0x0020 I2C_1CLK
06c0 (I2C Ch.1 Clock
Control Register)
AP-A-46
Bit Bit name
15–8 –
7 BSY
6 MMABSY
5–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
15–8 –
7–4 –
3–0 FRLDMAEN[3:0]
15–8 –
7–4 –
3–0 TCSH[3:0]
15–4 RMADR[31:20]
3-0 –
15–12 DUMDL[3:0]
11–8 DUMLN[3:0]
7–6 DATTMOD[1:0]
5–4 DUMTMOD[1:0]
3–2 ADRTMOD[1:0]
1 ADRCYC
0 MMAEN
15–8 XIPACT[7:0]
7–0 XIPEXT[7:0]
Bit Bit name
15–9 –
8 DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
Seiko Epson Corporation
Initial Reset R/W
0x00 – R
0 H0 R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x000 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0x0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 H0 R/W
0x00 H0 R/W
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
S1C31D50/D51 TECHNICAL MANUAL
Remarks
–
Cleared by writing 1.
Cleared by reading the
QSPI_0RXD register.
Cleared by writing to the
QSPI_0TXD register.
–
–
–
–
–
–
–
–
I C (I2C) Ch.1
2
Remarks
–
(Rev. 2.00)