Qspi Ch.n Mode Byte Register - Epson S1C31D50 Technical Manual

Bits 5–4 DUMTMOD[1:0]
These bits select the transfer mode for the dummy cycle when accessing the external Flash memory in
the memory mapped access mode.
Bits 3–2 ADRTMOD[1:0]
These bits select the transfer mode for the address cycle when accessing the external Flash memory in
the memory mapped access mode.
Bit 1 ADRCYC
This bit selects the address mode from 24 and 32 bits when accessing the external Flash memory in
the memory mapped access mode.
1 (R/W): 32-bit address mode (4-byte address cycle)
0 (R/W): 24-bit address mode (3-byte address cycle)
Bit 0 MMAEN
This bit enables memory mapped access mode for accessing the external Flash memory.
1 (R/W): Enable memory mapped access mode
0 (R/W): Disable memory mapped access mode (register access mode)
When this bit is altered from 1 to 0, the QSPI sends extra address and dummy cycles to the external
Flash memory. The address cycle outputs either a three or four-byte address according to the QSPI_
nMMACFG2.ADRCYC bit setting, with all address bits set to 1. The dummy cycle is output accord-
ing to the QSPI_nMMACFG2.DUMLN[3:0] and QSPI_nMMACFG2.DUMDL[3:0] bit settings, with
a mode byte for terminating the XIP session of the external Flash memory that has been configured
using the QSPI_nMB.XIPEXT[7:0] bits.
Note: Slave mode does not support memory mapped access mode, therefore, setting the QSPI_
nMMACFG2.MMAEN bit to 1 does not take effect when the QSPI_nMOD.MST bit = 0.

QSPI Ch.n Mode Byte Register

Register name Bit
QSPI_nMB 15–8 XIPACT[7:0]
7–0 XIPEXT[7:0]
Bits 15–8 XIPACT[7:0]
These bits configure the mode byte for activating an XIP session of the external Flash memory to be
accessed in memory mapped access mode.
Bits 7–0 XIPEXT[7:0]
These bits configure the mode byte for terminating the XIP session of the external Flash memory be-
ing accessed in memory mapped access mode.
Note: In memory mapped access mode, the mode byte is always output from the LSB first. When us-
ing a Flash memory that expects the mode byte to be output from the MSB first, write the mode
byte to this register in reverse bit order.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x00
Seiko Epson Corporation
15 Quad Synchronous Serial Interface (QSPI)
Reset R/W
H0 R/W –
H0 R/W
Remarks
15-37