Memory Check Function Register; Function Id Register; Interrupt Mask Register; Memory Address Register - Epson S1C31D50 Technical Manual

21.6.2 Memory Check Function Register

Function ID Register

Register name Bit
FUNCTION 15–8 –
7–0 ID[7:0]
Bits 15–8 Reserved
Set to 0x00 when writing data to this register.
Bits 7–0 ID[7:0]
These bits select the function to be executed in the HWP. (Refer to Table 21.6.2.)
Set to 0x03 when executing the memory check function.

Interrupt Mask Register

Register name Bit
INTMASK 15–8 –
(Memory Check)
7–2 –
1
0
Bits 15–2 Reserved
Set to 0x000(0) when writing data to this register.
Bit 1 TO_PROCESSING
Bit 0 TO_IDLE
These bits set whether the interrupt request when a state transition occurs during executing the memo-
ry check function is enabled or not.
1 (W): Enable interrupt
0 (W): Mask interrupt (disabled)
For more information on the state transition interrupts that can be masked with these bits, refer to
Table 21.5.2.

Memory Address Register

Register name Bit
MEMADDR 31–0 ADDRESS[31:0]
(Memory Check)
Bits 31–0 ADDRESS[31:0]
These bits specify the memory check start address.
The address should be specified within the range shown below.
In case of RAM:
0x15 0000, ..., 0x15 1fff
0x15 3000, ..., 0x15 67ff
In case of internal Flash:
0x00 0000, ..., 0x02 ffff
In case of external QSPI-Flash:
0x00 0000 + OFFSET, ..., 0x0f ffff + OFFSET
* The OFFSET is 0x04 0000, the start address of the memory mapped access area for external Flash
memory (refer to "Figure 4.1.1 Memory Map").
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x00
Bit name Initial
0x00
0x00
TO_PROCESSING 0
TO_IDLE 0
Bit name Initial
0x0000
0000
Seiko Epson Corporation
21 HW Processor (HWP) and Sound Output
Reset R/W
– R –
H0 W
Reset R/W
– R –
– R
H0 W
H0 W
Reset R/W
H0 W –
Remarks
Remarks
Remarks
21-23