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6. Set the INITVALUE.INITVALUE[31:0] bits to 0x00000000.
* It is not necessary in the RAM check.
7. Write 1 to the HWPCMDTRG.HWP0TRG bit.
8. Wait until the HWPINTF.HWP0IF bit is set to 1 (interrupt).
9. Confirm that the STATE.STATE[15:0] bits = transit destination state (if necessary).
RAM check
The following shows the procedure to execute a RAM check:
1. Confirm that the STATE.STATE[15:0] bits = 0x0001 (mc_state_idle).
2. Confirm that the STATUS.READY bit = 1.
3. Set the COMMAND.COMMAND[7:0] bits or 0x02 or 0x03.*
4. Set the MEMADDR.ADDRESS[31:0] bits.
5. Set the MEMSIZE.SIZE[31:0] bits.
6. Write 1 to the HWPCMDTRG.HWP0TRG bit.
7. Wait until the HWPINTF.HWP0IF bit is set to 1 (interrupt).
The HWP starts the memory check from this point.
8. Confirm that the STATE.STATE[15:0] bits = 0x0002 (mc_state_ram_rw) or 0x0003 (mc_state_ram_
march_c) as necessary.*
9. Write 0 to the HWPINTF.HWP0IF bit.
:
The memory check is in progress.
:
10. Wait until the HWPINTF.HWP0IF bit is set to 1 (interrupt).
The memory check is completed at this point.
11. Confirm that the STATE.STATE[15:0] bits = 0x0001 (mc_state_idle).
12. Write 0 to the HWPINTF.HWP0IF bit.
13. Read the STATUS.PROCESSING[1:0] bits.
When the STATUS.PROCESSING[1:0] bits = 0x2, the check has completed without an error. So the processing
can be terminated.
If the STATUS.PROCESSING[1:0] bits = 0x3, an error has occurred. In this case, confirm the address where
the error has occurred as follows:
14. Read the RESULT.RESULT[31:0] bits.
These bits hold the address where an error has occurred first.
* Two RAM check commands are available. Setting the COMMAND.COMMAND[7:0] bits to 0x02 selects
the RAM Check R/W Start command; setting to 0x03 selects the RAM Check March-C Start command.
RAM Check R/W Start command
When this command is issued by the trigger bit, the HWP transits to mc_state_ram_rw state to execute
the RAM read/write check. In this check, the HWP performs read-after-write verification for all addresses
twice: first it writes 0x55aa, next 0xaa55.
RAM Check March-C Start command
When this command is issued by the trigger bit, the HWP transits to mc_state_ram_march_c state to ex-
ecute the RAM marching test (March-C algorithm).
Note: When an error occurs during RAM check, the check is terminated at the address where the error
has occurred.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
21 HW Processor (HWP) and Sound Output
Seiko Epson Corporation
(Specify Flash check initial value)
(Trigger to issue command)
(Occurrence of state transition)
(Command acceptable)
(Select command)
(Specify check start address)
(Specify check size (byte))
(Trigger to issue command)
(Occurrence of state transition)
(Clear interrupt flag)
(Occurrence of state transition)
(Clear interrupt flag)
(Confirm check result)
(Confirm error address)
21-15
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