Epson S1C31D50 Technical Manual page 396

APPENDIX A LIST OF PERIPHERAL CIRCUIT CONTROL REGISTERS
0x0020 03b0–0x0020 03be
Address Register name
0x0020 SPIA_0MOD
03b0 (SPIA Ch.0 Mode
Register)
0x0020 SPIA_0CTL
03b2 (SPIA Ch.0 Control
Register)
0x0020 SPIA_0TXD
03b4
(SPIA Ch.0 Transmit
Data Register)
0x0020 SPIA_0RXD
03b6 (SPIA Ch.0 Receive
Data Register)
0x0020 SPIA_0INTF
03b8
(SPIA Ch.0 Interrupt
Flag Register)
0x0020 SPIA_0INTE
03ba (SPIA Ch.0 Interrupt
Enable Register)
0x0020 SPIA_0TBEDMAEN
03bc
(SPIA Ch.0 Transmit
Buffer Empty DMA
Request Enable
Register)
0x0020 SPIA_0RBFDMAEN
03be (SPIA Ch.0 Receive
Buffer Full DMA
Request Enable
Register)
0x0020 03c0–0x0020 03d6
Address Register name
0x0020 I2C_0CLK
03c0 (I2C Ch.0 Clock
Control Register)
0x0020 I2C_0MOD
03c2
(I2C Ch.0 Mode
Register)
AP-A-32
Bit Bit name
15–12 –
11–8 CHLN[3:0]
7–6 –
5 PUEN
4 NOCLKDIV
3 LSBFST
2 CPHA
1 CPOL
0 MST
15–8 –
7–2 –
1 SFTRST
0 MODEN
15–0 TXD[15:0]
15–0 RXD[15:0]
15–8 –
7 BSY
6–4 –
3 OEIF
2 TENDIF
1 RBFIF
0 TBEIF
15–8 –
7–4 –
3 OEIE
2 TENDIE
1 RBFIE
0 TBEIE
15–8 –
7–4 –
3–0 TBEDMAEN[3:0]
15–8 –
7–4 –
3–0 RBFDMAEN[3:0]
Bit Bit name
15–9 –
8 DBRUN
7–6 –
5–4 CLKDIV[1:0]
3–2 –
1–0 CLKSRC[1:0]
15–8 –
7–3 –
2 OADR10
1 GCEN
0 –
Seiko Epson Corporation
Synchronous Serial Interface (SPIA) Ch.0
Initial Reset R/W
0x0 – R
0x7 H0 R/W
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0x0000 H0 R/W
0x0000 H0 R
0x00 – R
0 H0 R
0x0 – R
0 H0/S0 R/W
0 H0/S0 R/W
0 H0/S0 R
1 H0/S0 R
0x00 – R
0x0 – R
0 H0 R/W
0 H0 R/W
0 H0 R/W
0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
0x00 – R
0x0 – R
0x0 H0 R/W
Initial Reset R/W
0x00 – R
0 H0 R/W
0x0 – R
0x0 H0 R/W
0x0 – R
0x0 H0 R/W
0x00 – R
0x00 – R
0 H0 R/W
0 H0 R/W
0 – R
S1C31D50/D51 TECHNICAL MANUAL
Remarks
–
–
–
–
–
Cleared by writing 1.
Cleared by reading the
SPIA_0RXD register.
Cleared by writing to the
SPIA_0TXD register.
–
–
–
I C (I2C) Ch.0
2
Remarks
–
–
(Rev. 2.00)