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Buzzer S1C31D51
Epson Buzzer S1C31D51 Manuals
Manuals and User Guides for Epson Buzzer S1C31D51. We have
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Epson Buzzer S1C31D51 manuals available for free PDF download: Technical Manual, Manual, Getting Started
Epson Buzzer S1C31D51 Technical Manual (425 pages)
CMOS 32-BIT SINGLE CHIP
Brand:
Epson
| Category:
Microcontrollers
| Size: 11.47 MB
Table of Contents
4
Table of Contents
16
1 Overview
16
Features
18
Block Diagram
19
Pins
19
Pin Configuration Diagram
23
Pin Descriptions
27
2 Power Supply, Reset, and Clocks
27
Power Generator (PWGA)
27
Overview
27
Pins
28
D1 Regulator Operation Mode
28
D1 Regulator Voltage Mode
29
System Reset Controller (SRC)
29
Overview
30
Input Pin
30
Reset Sources
31
Initialization Conditions (Reset Groups)
31
Clock Generator (CLG)
31
Overview
32
Input/Output Pins
32
Clock Sources
35
Operations
39
Operating Mode
39
Initial Boot Sequence
39
Transition between Operating Modes
41
Interrupts
41
Control Registers
41
PWGA Control Register
42
CLG System Clock Control Register
43
CLG Oscillation Control Register
44
CLG IOSC Control Register
44
CLG OSC1 Control Register
45
CLG OSC3 Control Register
47
CLG Interrupt Flag Register
47
CLG Interrupt Enable Register
48
CLG FOUT Control Register
49
3 CPU and Debugger
49
Overview
49
CPU Core
49
Debugger
49
List of Debugger Input/Output Pins
49
External Connection
50
4 Memory and Bus
50
Overview
51
Bus Access Cycle
51
Flash Memory
51
Flash Memory Pin
51
Flash Bus Access Cycle Setting
51
Flash Programming
52
Ram
52
Peripheral Circuit Control Registers
58
System-Protect Function
58
Instruction Cache
59
Memory Mapped Access Area for External Flash Memory
59
Control Registers
59
System Protect Register
59
CACHE Control Register
59
FLASHC Flash Read Cycle Register
60
5 Interrupt
60
Overview
60
Vector Table
62
Vector Table Offset Address (VTOR)
62
Priority of Interrupts
62
Peripheral Circuit Interrupt Control
63
Nmi
64
6 DMA Controller (DMAC)
64
Overview
65
Operations
65
Initialization
65
Priority
65
Data Structure
66
Transfer Source End Pointer
66
Transfer Destination End Pointer
66
Control Data
68
DMA Transfer Mode
68
Basic Transfer
68
Auto-Request Transfer
69
Ping-Pong Transfer
70
Memory Scatter-Gather Transfer
71
Peripheral Scatter-Gather Transfer
72
DMA Transfer Cycle
72
Interrupts
73
Control Registers
73
DMAC Status Register
73
DMAC Configuration Register
74
DMAC Control Data Base Pointer Register
74
DMAC Alternate Control Data Base Pointer Register
74
DMAC Software Request Register
74
DMAC Request Mask Set Register
75
DMAC Request Mask Clear Register
75
DMAC Enable Set Register
75
DMAC Enable Clear Register
75
DMAC Primary-Alternate Set Register
76
DMAC Primary-Alternate Clear Register
76
DMAC Priority Set Register
76
DMAC Priority Clear Register
76
DMAC Error Interrupt Flag Register
77
DMAC Transfer Completion Interrupt Flag Register
77
DMAC Transfer Completion Interrupt Enable Set Register
77
DMAC Transfer Completion Interrupt Enable Clear Register
77
DMAC Error Interrupt Enable Set Register
78
DMAC Error Interrupt Enable Clear Register
79
7 O Ports (PPORT)
79
Overview
80
I/O Cell Structure and Functions
80
Schmitt Input
81
Over Voltage Tolerant Fail-Safe Type I/O Cell
81
Pull-Up/Pull-Down
81
CMOS Output and High Impedance State
81
Clock Settings
81
PPORT Operating Clock
81
Clock Supply in SLEEP Mode
82
Clock Supply During Debugging
82
Operations
82
Initialization
83
Port Input/Output Control
84
Interrupts
85
Control Registers
85
Px Port Data Register
85
Px Port Enable Register
86
Px Port Pull-Up/Down Control Register
86
Px Port Interrupt Flag Register
86
Px Port Interrupt Control Register
87
Px Port Chattering Filter Enable Register
87
Px Port Mode Select Register
87
Px Port Function Select Register
88
P Port Clock Control Register
89
P Port Interrupt Flag Group Register
90
Control Register and Port Function Configuration of this IC
90
P0 Port Group
92
P1 Port Group
95
P2 Port Group
97
P3 Port Group
99
P4 Port Group
102
P5 Port Group
104
P6 Port Group
106
P7 Port Group
109
P8 Port Group
111
P9 Port Group
113
Pa Port Group
115
Pd Port Group
117
Common Registers between Port Groups
118
8 Universal Port Multiplexer (UPMUX)
118
Overview
118
Peripheral Circuit I/O Function Assignment
119
Control Registers
119
Pxy-Xz Universal Port Multiplexer Setting Register
120
9 Watchdog Timer (WDT2)
120
Overview
120
Clock Settings
120
WDT2 Operating Clock
120
Clock Supply in DEBUG Mode
121
Operations
121
WDT2 Control
122
Operations in HALT and SLEEP Modes
122
Control Registers
122
WDT2 Clock Control Register
123
WDT2 Control Register
123
WDT2 Counter Compare Match Register
125
10 Real-Time Clock (RTCA)
125
Overview
125
Output Pin and External Connection
125
Output Pin
126
Clock Settings
126
RTCA Operating Clock
126
Theoretical Regulation Function
127
Operations
127
RTCA Control
128
Real-Time Clock Counter Operations
128
Stopwatch Control
128
Stopwatch Count-Up Pattern
129
Interrupts
130
Control Registers
130
RTCA Control Register (Low Byte)
131
RTCA Control Register (High Byte)
131
RTCA Second Alarm Register
132
RTCA Hour/Minute Alarm Register
132
RTCA Stopwatch Control Register
133
RTCA Second/1Hz Register
134
RTCA Hour/Minute Register
135
RTCA Month/Day Register
135
RTCA Year/Week Register
136
RTCA Interrupt Flag Register
137
RTCA Interrupt Enable Register
139
11 Supply Voltage Detector (SVD3)
139
Overview
140
Input Pins and External Connection
140
Input Pins
140
External Connection
140
Clock Settings
140
SVD3 Operating Clock
140
Clock Supply in SLEEP Mode
141
Clock Supply in DEBUG Mode
141
Operations
141
SVD3 Control
142
SVD3 Operations
142
SVD3 Interrupt and Reset
142
SVD3 Interrupt
143
SVD3 Reset
143
Control Registers
143
SVD3 Clock Control Register
144
SVD3 Control Register
145
SVD3 Status and Interrupt Flag Register
145
S1C31D50/D51 TECHNICAL MANUAL Seiko Epson Corporation
146
SVD3 Interrupt Enable Register
147
16 Bit Timers (T16)
147
Overview
147
Input Pin
148
Clock Settings
148
T16 Operating Clock
148
Clock Supply in SLEEP Mode
148
Clock Supply During Debugging
148
Event Counter Clock
148
Operations
149
Counter Underflow
149
Operations in Repeat Mode
149
Operations in One-Shot Mode
150
Counter Value Read
150
Interrupt
150
Control Registers
150
T16 Ch.n Clock Control Register
151
T16 Ch.n Control Register
152
T16 Ch.n Reload Data Register
152
T16 Ch.n Counter Data Register
152
T16 Ch.n Interrupt Flag Register
153
T16 Ch.n Interrupt Enable Register
154
13 Uart (Uart3)
154
Overview
155
Input/Output Pins and External Connections
155
List of Input/Output Pins
155
External Connections
155
Input Pin Pull-Up Function
155
Output Pin Open-Drain Output Function
155
Input/Output Signal Inverting Function
156
Clock Supply in SLEEP Mode
156
Clock Supply During Debugging
156
Baud Rate Generator
156
Data Format
157
Operations
157
Initialization
158
Data Transmission
159
Data Reception
161
Carrier Modulation
162
Receive Errors
162
Framing Error
162
Parity Error
162
Overrun Error
163
Interrupts
163
DMA Transfer Requests
164
Control Registers
164
UART3 Ch.n Clock Control Register
164
UART3 Ch.n Mode Register
166
UART3 Ch.n Baud-Rate Register
166
UART3 Ch.n Control Register
167
UART3 Ch.n Transmit Data Register
167
UART3 Ch.n Receive Data Register
167
UART3 Ch.n Status and Interrupt Flag Register
168
UART3 Ch.n Interrupt Enable Register
169
UART3 Ch.n Transmit Buffer Empty DMA Request Enable Register
169
UART3 Ch.n Receive Buffer One Byte Full DMA Request Enable Register
169
UART3 Ch.n Carrier Waveform Register
170
14 Synchronous Serial Interface (SPIA)
170
Overview
171
Input/Output Pins and External Connections
171
List of Input/Output Pins
171
External Connections
172
Pin Functions in Master Mode and Slave Mode
172
Input Pin Pull-Up/Pull-Down Function
172
Clock Settings
172
SPIA Operating Clock
173
Clock Supply During Debugging
173
SPI Clock (Spiclkn) Phase and Polarity
174
Data Format
174
Operations
174
Initialization
175
Data Transmission in Master Mode
177
Data Reception in Master Mode
179
Terminating Data Transfer in Master Mode
179
Data Transfer in Slave Mode
180
Terminating Data Transfer in Slave Mode
181
Interrupts
182
DMA Transfer Requests
182
Control Registers
182
SPIA Ch.n Mode Register
183
SPIA Ch.n Control Register
184
SPIA Ch.n Transmit Data Register
184
SPIA Ch.n Receive Data Register
184
SPIA Ch.n Interrupt Flag Register
185
SPIA Ch.n Interrupt Enable Register
185
SPIA Ch.n Transmit Buffer Empty DMA Request Enable Register
185
SPIA Ch.n Receive Buffer Full DMA Request Enable Register
186
15 Quad Synchronous Serial Interface (QSPI)
186
Overview
187
Input/Output Pins and External Connections
187
List of Input/Output Pins
187
External Connections
191
Pin Functions in Master Mode and Slave Mode
191
Input Pin Pull-Up/Pull-Down Function
191
Clock Settings
191
QSPI Operating Clock
192
Clock Supply During Debugging
192
QSPI Clock (Qspiclkn) Phase and Polarity
193
Data Format
194
Register Access Mode
195
Memory Mapped Access Mode
196
Initialization
197
Data Transmission in Master Mode
199
Data Reception in Register Access Master Mode
202
Data Reception in Memory Mapped Access Mode
210
Terminating Memory Mapped Access Operations
210
Terminating Data Transfer in Master Mode
211
Data Transfer in Slave Mode
212
Terminating Data Transfer in Slave Mode
212
Interrupts
213
DMA Transfer Requests
214
Control Registers
214
QSPI Ch.n Mode Register
216
QSPI Ch.n Control Register
217
QSPI Ch.n Transmit Data Register
217
QSPI Ch.n Receive Data Register
217
QSPI Ch.n Interrupt Flag Register
218
QSPI Ch.n Interrupt Enable Register
218
QSPI Ch.n Transmit Buffer Empty DMA Request Enable Register
219
QSPI Ch.n Receive Buffer Full DMA Request Enable Register
219
QSPI Ch.n FIFO Data Ready DMA Request Enable Register
220
QSPI Ch.n Remapping Start Address High Register
220
QSPI Ch.n Memory Mapped Access Configuration Register 2
222
QSPI Ch.n Mode Byte Register
223
100 C (I2C)
223
Overview
224
Input/Output Pins and External Connections
224
List of Input/Output Pins
224
External Connections
225
Clock Settings
225
I2C Operating Clock
225
Clock Supply During Debugging
225
Baud Rate Generator
226
Operations
226
Initialization
227
Data Transmission in Master Mode
229
Data Reception in Master Mode
232
10-Bit Addressing in Master Mode
233
Data Transmission in Slave Mode
235
Data Reception in Slave Mode
237
Slave Operations in 10-Bit Address Mode
237
Automatic Bus Clearing Operation
238
Error Detection
239
Interrupts
240
DMA Transfer Requests
240
Control Registers
240
I2C Ch.n Clock Control Register
241
I2C Ch.n Mode Register
241
I2C Ch.n Baud-Rate Register
242
I2C Ch.n Own Address Register
242
I2C Ch.n Control Register
243
I2C Ch.n Transmit Data Register
243
I2C Ch.n Receive Data Register
244
I2C Ch.n Status and Interrupt Flag Register
245
I2C Ch.n Interrupt Enable Register
246
I2C Ch.n Transmit Buffer Empty DMA Request Enable Register
246
I2C Ch.n Receive Buffer Full DMA Request Enable Register
247
16 Bit PWM Timers (T16B)
247
Overview
248
Input/Output Pins
249
Clock Settings
249
T16B Operating Clock
249
Clock Supply in SLEEP Mode
249
Clock Supply During Debugging
249
Event Counter Clock
250
Operations
250
Initialization
251
Counter Block Operations
254
Comparator/Capture Block Operations
263
TOUT Output Control
269
Interrupt
269
DMA Transfer Requests
269
Control Registers
269
T16B Ch.n Clock Control Register
270
T16B Ch.n Counter Control Register
271
T16B Ch.n Max Counter Data Register
271
T16B Ch.n Timer Counter Data Register
272
T16B Ch.n Counter Status Register
273
T16B Ch.n Interrupt Flag Register
274
T16B Ch.n Interrupt Enable Register
275
T16B Ch.n Comparator/Capture M Control Register
277
T16B Ch.n Compare/Capture M Data Register
278
T16B Ch.n Counter Max/Zero DMA Request Enable Register
278
T16B Ch.n Compare/Capture M DMA Request Enable Register
279
18 IR Remote Controller (REMC3)
279
Overview
279
Output Pins and External Connections
279
List of Output Pins
280
External Connections
280
Clock Settings
280
REMC3 Operating Clock
280
Clock Supply in SLEEP Mode
280
Clock Supply During Debugging
280
Operations
281
Data Transmission Procedures
281
REMO Output Waveform
283
Continuous Data Transmission and Compare Buffers
284
Interrupts
285
Application Example: Driving el Lamp
285
Control Registers
285
REMC3 Clock Control Register
286
REMC3 Data Bit Counter Control Register
287
REMC3 Data Bit Counter Register
288
REMC3 Data Bit Active Pulse Length Register
288
REMC3 Data Bit Length Register
288
REMC3 Status and Interrupt Flag Register
289
REMC3 Interrupt Enable Register
289
REMC3 Carrier Waveform Register
289
REMC3 Carrier Modulation Control Register
291
12 Bit A/D Converter (ADC12A)
291
Overview
292
Input Pins and External Connections
292
List of Input Pins
292
External Connections
292
Clock Settings
292
ADC12A Operating Clock
292
Sampling Time
293
Operations
293
Initialization
293
Conversion Start Trigger Source
294
Conversion Mode and Analog Input Pin Settings
294
A/D Conversion Operations and Control Procedures
296
Interrupts
296
DMA Transfer Requests
297
Control Registers
297
ADC12A Ch.n Control Register
298
ADC12A Ch.n Trigger/Analog Input Select Register
299
ADC12A Ch.n Configuration Register
300
ADC12A Ch.n Interrupt Flag Register
300
ADC12A Ch.n Interrupt Enable Register
301
ADC12A Ch.n DMA Request Enable Register M
301
ADC12A Ch.n Result Register
302
20 F Converter (RFC)
302
Overview
303
Input/Output Pins and External Connections
303
List of Input/Output Pins
303
External Connections
304
Clock Settings
304
RFC Operating Clock
304
Clock Supply in SLEEP Mode
304
Clock Supply in DEBUG Mode
304
Operations
304
Initialization
305
Operating Modes
305
RFC Counters
306
Converting Operations and Control Procedure
308
CR Oscillation Frequency Monitoring Function
308
Interrupts
309
Control Registers
309
RFC Ch.n Clock Control Register
309
RFC Ch.n Control Register
310
RFC Ch.n Oscillation Trigger Register
311
RFC Ch.n Measurement Counter Low and High Registers
311
RFC Ch.n Time Base Counter Low and High Registers
312
RFC Ch.n Interrupt Flag Register
312
RFC Ch.n Interrupt Enable Register
313
21 HW Processor (HWP) and Sound Output
313
Overview
315
Output Pins and External Connections
315
List of Output Pins
315
External Connections
316
Clock Settings
316
HWP Operating Clock
316
Clock Supply in SLEEP Mode
316
Clock Supply in DEBUG Mode
316
Operations
316
Sound Play Function
325
Memory Check Function
329
Interrupts
330
HWP Internal Registers
330
Sound Play Function Registers
330
Function ID Register
330
Interrupt Mask Register
331
ROM Address Register
331
ROM Size Register
331
Key Code Register
332
N Command Register
332
N Sentence Number Setting Register
332
N Volume Control Register
333
N Repeat Control Register
333
0 Playback Speed Conversion Register
334
N State Monitor Register
334
Error Status Register
334
Operating Status Register
334
Version Number Register
335
Memory Check Function Register
335
Function ID Register
335
Interrupt Mask Register
335
Memory Address Register
336
Memory Size Register
336
Initial Value Setting Register
336
Command Register
336
State Monitor Register
337
Error Status Register
337
Operating Status Register
337
Calculation Result Register
337
Version Number Register
338
Control Registers
338
HWP Control Register
338
HWP Interrupt Flag Register
338
HWP Interrupt Enable Register
338
HWP Command Trigger Register
339
SDAC Clock Control Register
339
SDAC Control Register
340
SDAC Mode Register
340
SDAC Data Register
340
SDAC Interrupt Flag Register
341
SDAC Interrupt Enable Register
343
Current Consumption
345
System Reset Controller (SRC) Characteristics
346
Clock Generator (CLG) Characteristics
349
Flash Memory Characteristics
349
Input/Output Port (PPORT) Characteristics
350
Supply Voltage Detector (SVD3) Characteristics
352
UART (UART3) Characteristics
352
Synchronous Serial Interface (SPIA) Characteristics
354
Quad Synchronous Serial Interface (QSPI) Characteristics
354
I 2 C (I2C) Characteristics
356
R/F Converter (RFC) Characteristics
358
23 Basic External Connection Diagram
361
24 Package
365
Appendix A List of Peripheral Circuit Control Registers
365
System Register (SYS)
365
Power Generator (PWGA)
366
Cache Controller (CACHE)
367
0X0020 00C0-0X0020 00D2 Real-Time Clock (RTCA)
367
0X0020 0040-0X0020 0050Clock Generator (CLG)
369
0X0020 0160-0X0020 016C 16-Bit Timer (T16) Ch.0
369
0X0020 01B0 Flash Controller (FLASHC)
394
UART (UART3) Ch.0
395
0X0020 03A0-0X0020 03Ac 16-Bit Timer (T16) Ch.1
403
0X0020 04A0-0X0020 04Ac 16-Bit Timer (T16) Ch.4
403
0X0020 04C0-0X0020 04Cc 16-Bit Timer (T16) Ch.5
405
0X0020 0600-0X0020 0614 UART (UART3) Ch.1
405
UART (UART3) Ch.2
407
0X0020 0660-0X0020 066C 16-Bit Timer (T16) Ch.6
409
0X0020 0680-0X0020 068C 16-Bit Timer (T16) Ch.2
409
0X0020 0690-0X0020 06A8 Quad Synchronous Serial Interface (QSPI) Ch.0
413
0X0020 0720-0X0020 0732 IR Remote Controller (REMC3)
415
0X0020 0840-0X0020 0850 R/F Converter (RFC) Ch.0
417
0X0020 08A0-0X0020 08A8 HW Processor (HWP)
417
0X0020 1000-0X0020 2014 DMA Controller (DMAC)
Advertisement
Epson Buzzer S1C31D51 Manual (21 pages)
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
Brand:
Epson
| Category:
Motherboard
| Size: 2.24 MB
Table of Contents
3
Table of Contents
5
1 Overview
6
2 Name and Function of each Part
8
3 Settings
8
Jumpers
11
Power Supply
12
Audio Amplifier
13
Buzzer Speech
14
4 Usage
14
Running Demo Software
15
Debugging Software
16
Appendix A Circuit Diagrams
19
Appendix B Parts List
20
Revision History
Epson Buzzer S1C31D51 Manual (15 pages)
CMOS 32-BIT SINGLE CHIP MICROCONTROLLER
Brand:
Epson
| Category:
Motherboard
| Size: 1.71 MB
Table of Contents
3
Table of Contents
5
1 Overview
6
2 Name and Function of each Part
7
3 Settings
7
Jumpers
7
Resistors
7
Connectors
8
Jumper Settings for S1C31D51 Evaluation Board (S5U1C31D51T1)
9
4 Usage
9
Running of the Demo Software
10
Appendix A Circuit Diagrams
11
Appendix B Parts List
12
Appendix C Recommended Circuit for Buzzer Connection
12
Recommended Circuit for Electromagnetic Buzzer Connection
13
Recommended Circuit for Piezoelectric Buzzer Connection
14
Revision History
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Epson Buzzer S1C31D51 Getting Started (13 pages)
Sound MCU
Brand:
Epson
| Category:
Motherboard
| Size: 1.92 MB
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