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2.2.4 Initialization Conditions (Reset Groups)
A different initialization condition is set for the CPU registers and peripheral circuit control bits, individually. The
reset group refers to an initialization condition. Initialization is performed when a reset source included in a reset
group issues a reset request. Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con-
trol bits, refer to the "CPU and Debugger" chapter or "Control Registers" in each peripheral circuit chapter.
Reset group
H0
H1
S0
2.3 Clock Generator (CLG)
2.3.1 Overview
CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- IOSC oscillator circuit that oscillates with a fast startup and no external parts required
- Low-power OSC1 oscillator circuit in which the oscillator type can be specified from high-precision 32.768
kHz crystal oscillator (an external resonator is required) and internal oscillator
- 16 MHz (max.) high-speed OSC3 oscillator circuit in which the oscillator type can be specified from crystal/
ceramic oscillator (an external resonator is required) and internal oscillator
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals up to 16 MHz
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the peripheral cir-
cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mode cancelation.
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
• Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal
state.
Figure 2.3.1.1 shows the CLG configuration.
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 2.2.4.1 List of Reset Groups
Reset source
#RESET pin
POR and BOR
Reset request from the CPU
Supply voltage detector reset
Watchdog timer reset
#RESET pin
POR and BOR
Reset request from the CPU
Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations de-
pend on the peripheral circuit.
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset cancelation timing
Reset state is maintained for the reset
hold time t
after the reset request is
RSTR
canceled.
Reset state is canceled immediately
after the reset request is canceled.
2-5
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