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2
21 i
C SlaVe (i2CS)
The I2CS input/output pins (SDA1, SCL1, #BFR) are shared with I/O ports and are initially set as general purpose
I/O port pins. The pin functions must be switched using the port function select bits to use the general purpose I/O
port pins as I2CS input/output pins. For detailed information on pin function switching, see the "I/O Ports (P)" chap-
ter.
note: The pins go to high impedance status when the port function is switched.
The SCL1 and SDA1 pins do not output a high level, so these lines should be pulled up to V
with an external pull-up resistor. Be sure to avoid pulling these pins up to a voltage that exceeds
the V
level.
DD
21.3
Operation Clock
The I2CS module operates with the clock output from the external I
pin.
The I2CS module also uses the peripheral module clock (PCLK) for its operations. The PCLK frequency must be
set eight-times or higher than the SCL1 input clock frequency during data transfer. In standby status, use of the
asynchronous address detection function allows the application to lower the PCLK clock frequency to reduce cur-
rent consumption. For more information, see "Asynchronous address detection function" in Section 21.4.3.
21.4
initializing i2CS
21.4.1
Reset
The I2CS module must be reset to initialize the communication process and to set the I
impedance). The following shows two methods for resetting the module:
(1) Software reset
The I2CS module can be reset using SOFTRESET/I2CS_CTL register.
To reset the I2CS module, write 1 to SOFTRESET to place the I2CS module into reset status, then write 0 to
SOFTRESET to release it from reset status. It is not necessary to insert a waiting time between writing 1 and 0.
The I2CS module initializes the I
pedance to be ready to detect a start condition. Furthermore, the I2CS control bits except for SOFTRESET are
initialized. Perform the software reset in the initial setting process before staring communication.
(2) Bus free request with an input from the #BFR pin
The I2CS module can accept bus free requests via the #BFR pin. The bus free request support is disabled by
default. To enable this function, set BFREQ_EN/I2CS_CTL register to 1.
When this function is enabled, a low pulse (One peripheral module clock (PCLK) cycles or more pulse width is
required. Two PCLK clock cycles or more pulse width is recommended.) input to the #BFR pin sets BFREQ/
I2CS_STAT register to 1. This initializes the I
into high-impedance. The control registers will not be initialized as distinct from the software reset described
above.
note: When BFREQ is set to 1 (an interrupt can be used for checking this status), perform a software
reset and set the registers again.
21-2
2
I
C master
SDA1
I2CS
2
Figure 21.
2.1 I
C Connection Example
2
C communication process and put the SDA1 and SCL1 pins into high-im-
2
C communication process and puts the SDA1 and SCL1 pins
Seiko epson Corporation
V
DD
SCL1
2
I
C slave
2
C master device by inputting it from the SCL1
S1C17624/604/622/602/621 TeChniCal Manual
DD
2
C bus into free status (high
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