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6 DMA Controller (DMAC)
6.1 Overview
The main features of the DMAC are outlined below.
• Supports byte, halfword, and word transfers.
• Each DMAC channel can be configured to different transfer conditions independently.
• Supports memory-to-memory, memory-to-peripheral circuit, and peripheral circuit-to-memory transfers.
• Supports hardware DMA requests from peripheral circuits and software DMA requests.
• Priority level for each channel is selectable from two levels.
• DMA transfers are allowed even if the CPU is placed into HALT mode.
Figure 6.1.1 shows the configuration of the DMAC.
Item
Number of channels
Transfer source memories
Transfer destination memories
Transfer source peripheral circuits
Transfer destination peripheral circuits
DMAC
MSTEN
CPTRn
RMSETn
RMCLRn
ENSETn
ENCLRn
PASETn
PACLRn
PRSETn
PRCLRn
CPU core
ENDIESETn
ENDIECLRn
ERRIESET
ERRIECLR
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Table 6.1.1 DMAC Channel Configuration of S1C31D50/D51
48-pin package
Internal Flash memory, external Flash memory, and RAM
Ch.n
DMA transfer
control circuit
Interrupt
control circuit
Figure 6.1.1 DMAC Configuration
Seiko Epson Corporation
64-pin package
80-pin package
4 channels (Ch.0 to Ch.3)
RAM
UART3, SPIA, QSPI, I2C, T16B, and ADC12A
UART3, SPIA, QSPI, I2C, and T16B
CHNLS[4:0]
STATE[3:0]
MSTENSTAT
ACPTRn
Bus matrix
Peripheral circuit
SWREQn
DMA transfer request
Peripheral circuit
ENDIFn
DMA transfer request
ERRIF
6 DMA CONTROLLER (DMAC)
100-pin package
Flash memory,
RAM, etc.
6-1
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